# US 11,443,815 B2 · Memory device and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,815 B2 - Document ID: US11443815B2 - Status: Granted - Kind: B2 - Application number: 17/145,828 - Filed: 2021-01-11 - Published: 2022-01-27 - Granted: 2022-09-13 - Earliest claimed: 2020-07-24 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jae Hyeon Shin; Gwi Han Ko; Sung Hun Kim; Gwan Park; Hyun Soo Lee - Web page: https://patentgrep.com/patent/US11443815B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0425: {comprising cells containing a merged floating gate and select transistor} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/30: Power supply circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines. ## Claims ### Claim 1 A memory device, comprising: a first sub-block including a plurality of first select transistors and a plurality of first memory cells; a second sub-block coupled to the first sub-block through a plurality of word lines and including a plurality of second select transistors and a plurality of second memory cells; a peripheral circuit configured to perform a read operation on data stored in the first sub-block or the second sub-block; and a control logic configured to control the peripheral circuit to apply a read voltage to a selected word line among the plurality of word lines, wherein, when the read operation is performed on the first sub-block, the control logic controls the peripheral circuit to: turn on the plurality of first select transistors and the plurality of second select transistors, increase a voltage level of the plurality of word lines from a first level to a second level, turn off the plurality of second select transistors when the voltage level of the plurality of word lines reaches the second level, and increase the voltage level of the plurality of word lines from the second level to a third level. ### Claim 2 (depends on 1) The memory device of claim 1, wherein, after increasing the voltage level of the plurality of word lines to the third level, the control logic controls the peripheral circuit to decrease the voltage level of the selected word line to a read voltage level. ### Claim 3 (depends on 1) The memory device of claim 1, wherein, after increasing the voltage level of the plurality of word lines to the third level, the control logic controls the peripheral circuit to: decrease the voltage level of the selected word line from the third level to the first level, and increase the voltage level of the selected word line to a read voltage level. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the control logic controls the peripheral circuit to apply a precharge voltage to a plurality of bit lines coupled to the first sub-block after increasing the voltage level of the plurality of word lines to the third level. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the first level is a voltage level greater than 0 V. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the third level is a voltage level for turning on the plurality of memory cells. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the control logic controls the peripheral circuit to turn off the second select transistors included in the second sub-block when the voltage level of a word line farthest away from a point where a voltage is supplied, among the plurality of word lines, reaches the second level. ### Claim 8 A method of operating a memory device including a first sub-block including a plurality of first select transistors and a plurality of first memory cells, and a second sub-block coupled to the first sub-block through a plurality of word lines and including a plurality of second select transistors and a plurality of second memory cells, the memory device performing a read operation on the first sub-block, the method comprising: turning on the plurality of first select transistors and the plurality of second select transistors; increasing a voltage level of the plurality of word lines from a first level to a second level; turning off the plurality of second select transistors; and increasing the voltage level of the plurality of word lines from the second level to a third level. ### Claim 9 (depends on 8) The method of claim 8, further comprising applying a read voltage to a selected word line among the plurality of word lines. ### Claim 10 (depends on 9) The method of claim 9, wherein the applying of the read voltage comprises decreasing the voltage level of the selected word line to a read voltage level after increasing the voltage level of the plurality of word lines to the third level. ### Claim 11 (depends on 9) The method of claim 9, wherein the applying of the read voltage comprises: decreasing the voltage level of the selected word line to the first level after increasing the voltage level of the plurality of word lines to the third level, and increasing the voltage level of the selected word line to a read voltage level after decreasing the voltage level of the selected word line to the first level. ### Claim 12 (depends on 8) The method of claim 8, further comprising applying a precharge voltage to a plurality of bit lines coupled to the first sub-block after increasing the voltage level of the plurality of word lines to the third level. ### Claim 13 (depends on 8) The method of claim 8, wherein the first level is a voltage level greater than 0 V. ### Claim 14 (depends on 8) The method of claim 8, wherein the third level is a voltage level for turning on the plurality of first memory cells and the plurality of second memory cells. ### Claim 15 A memory device, comprising: a first sub-block including a plurality of first select transistors and a plurality of first memory cells; a second sub-block coupled to the first sub-block through a plurality of word lines and including a plurality of second select transistors and a plurality of second memory cells; and a peripheral circuit performing a read operation on data stored in the first sub-block or the second sub-block, wherein, in configured to perform the read operation, the peripheral circuit turns on the plurality of first select transistors and the plurality of second select transistors, increases a voltage level of the plurality of word lines in stepwise increments including at least two stepped increases, and turns off the plurality of second select transistors when the voltage level of the plurality of word lines reaches a target voltage level. ### Claim 16 (depends on 15) The memory device of claim 15, wherein, in performing the read operation, the peripheral circuit decreases a voltage level of the selected word line to a read voltage level after increasing the voltage level of the plurality of word lines in stepwise increments. ### Claim 17 (depends on 15) The memory device of claim 15, wherein, in performing the read operation, the peripheral circuit decreases a voltage level of the selected word line to a ground voltage level and increases the voltage level of the selected word line from the ground voltage level to a read voltage level after increasing the voltage level of the plurality of word lines in stepwise increments. ### Claim 18 (depends on 15) The memory device of claim 15, wherein, in performing the read operation, the peripheral circuit applies a precharge voltage to a plurality of bit lines coupled to the first sub-block after increasing the voltage level of the plurality of word lines in stepwise increments. ### Claim 19 (depends on 15) The memory device of claim 15, wherein, in performing the read operation, the peripheral circuit increases the voltage level of the plurality of word lines to a pass voltage level in one of the stepwise increments, the pass voltage level for turning on the plurality of first memory cells and the plurality of second memory cells. ### Claim 20 (depends on 15) The memory device of claim 15, wherein the peripheral circuit turns off the plurality of second select transistors when the voltage level of a word line farthest away from a point where a voltage is supplied, among the plurality of word lines, reaches the target voltage level.