# US 11,443,813 B2 · Methods for erase and reset in a three-dimensional NAND flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,813 B2 - Document ID: US11443813B2 - Status: Granted - Kind: B2 - Application number: 17/159,354 - Filed: 2021-01-27 - Published: 2022-06-09 - Granted: 2022-09-13 - Earliest claimed: 2020-12-04 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Qiang Tang; Li Wei Wang - Web page: https://patentgrep.com/patent/US11443813B2 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 11/5635: {Erasing circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/32: Timing circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Methods for erasing storage data of a three-dimensional (3D) memory device are presented. The 3D memory device includes a plurality of memory blocks, each memory block having a plurality of memory strings with vertically stacked memory cells. Each memory cell is addressable through a word line and a bit line. The storage data in a selected memory block can be erased by applying an erase voltage on an array common source and applying a first voltage on the word lines of the selected memory block. Word lines of an unselected memory block are floating, i.e., without external bias, during the erasing operation. After the erasing operation, a second voltage is applied on the word lines of entire memory plane to reset the memory cells for improved data retention. ## Claims ### Claim 1 A method for operating a three-dimensional (3D) memory device comprising memory blocks, wherein each memory block comprises memory strings with vertically stacked memory cells, and wherein each vertically stacked memory cell is addressable through a word line and a bit line, the method comprising: performing an erase operation on a selected memory block; inhibiting the erase operation on an unselected memory block; and applying a reset voltage on word lines of the unselected memory block to reset the unselected memory block after performing the erase operation. ### Claim 2 (depends on 1) The method of claim 1, wherein the performing the erase operation on the selected memory block comprises: applying an erase voltage on an array common source of the selected memory block; and applying a first voltage on word lines of the selected memory block, wherein the first voltage is less than the erase voltage to thereby erase the selected memory block. ### Claim 3 (depends on 2) The method of claim 2, wherein the applying the first voltage comprises applying a voltage in a range between about 0 V and about 1 V. ### Claim 4 (depends on 2) The method of claim 2, wherein the applying the first voltage comprises applying a voltage of about 0 V. ### Claim 5 (depends on 2) The method of claim 2, wherein the applying the erase voltage comprises applying a voltage in a range between about 15 V to about 25 V. ### Claim 6 (depends on 2) The method of claim 2, further comprising: resetting the selected memory block after performing the erase operation, the resetting comprising applying the reset voltage on the word lines of the selected memory block. ### Claim 7 (depends on 6) The method of claim 6, further comprising: applying a voltage of about 0 V on the array common source of the selected memory block after performing the erase operation. ### Claim 8 (depends on 2) The method of claim 2, further comprising: prior to performing the erase operation, applying a voltage of about 0 V on the word lines of the selected memory block; and subsequently removing the voltage of about 0 V from the word lines of the selected memory block such that the word lines of the selected memory block are floating without an external bias. ### Claim 9 (depends on 1) The method of claim 1, wherein applying the reset voltage comprises applying a voltage in a range between about 1.5 V to about 3.5 V. ### Claim 10 (depends on 1) The method of claim 1, wherein the inhibiting the erase operation on the unselected memory block comprises floating the word lines of the unselected memory block without an external voltage. ### Claim 11 (depends on 1) The method of claim 1, wherein the inhibiting the erase operation on the unselected memory block further comprises floating an array common source of the unselected memory block. ### Claim 12 A three-dimensional (3D) memory device, comprising: a memory block, comprising memory cells, wherein each of the memory cells is addressable through a word line and a bit line; and a peripheral circuit, configured to: perform an erase operation on a selected memory block; inhibit the erase operation on an unselected memory block; and apply a reset voltage on word lines of the unselected memory block to reset the unselected memory block after performing the erase operation. ### Claim 13 (depends on 12) The 3D memory device of claim 12, wherein during the erase operation, the peripheral circuit is further configured to: apply an erase voltage on an array common source of the selected memory block; and apply a first voltage on word lines of the selected memory block, wherein the first voltage is less than the erase voltage to thereby erase the selected memory block. ### Claim 14 (depends on 13) The 3D memory device of claim 13, wherein the first voltage comprises a voltage in a range between about 0 V and about 1 V. ### Claim 15 (depends on 13) The 3D memory device of claim 13, wherein the first voltage is a voltage of about 0 V. ### Claim 16 (depends on 13) The 3D memory device of claim 13, wherein the erase voltage comprises a voltage in a range between about 15 V to about 25 V. ### Claim 17 (depends on 12) The 3D memory device of claim 12, wherein the periphery circuit is further configured to: reset the selected memory block after performing the erase operation, wherein the reset voltage is applied on word lines of the selected memory block. ### Claim 18 (depends on 17) The 3D memory device of claim 17, wherein the reset voltage comprises a voltage in a range between about 1.5 V to about 3.5 V. ### Claim 19 (depends on 17) The 3D memory device of claim 17, wherein the periphery circuit is further configured to: apply a voltage of about 0 V on the word lines of the selected memory block prior to performing the erase operation; and remove the voltage of about 0 V from the word lines of the selected memory block subsequently such that the word lines of the selected memory block are floating without an external bias. ### Claim 20 (depends on 19) The 3D memory device of claim 19, wherein during inhibiting the erase operation on the unselected memory block, the periphery circuit is further configured to: float the word lines of the unselected memory block without an external voltage; and float an array common source of the unselected memory block.