# US 11,443,807 B2 · Memory device using comb-like routing structure for reduced metal line loading

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- Number: US 11,443,807 B2
- Document ID: US11443807B2
- Status: Granted
- Kind: B2
- Application number: 17/317,215
- Filed: 2021-05-11
- Published: 2021-09-02
- Granted: 2022-09-13
- Earliest claimed: 2018-09-10
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Zongliang Huo; Li Hong Xiao; Zhiliang Xia
- Web page: https://patentgrep.com/patent/US11443807B2

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 30/674: {characterised by the active materials}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.

## Claims

### Claim 1

A memory device, comprising:
a layer stack having alternating conductor and insulator layers; and
a first set of vertical structures and a second set of vertical structures extending vertically through the layer stack, wherein
the first set of vertical structures and the second set of vertical structures comprise a plurality of first ends and a plurality of second ends, wherein the plurality of first ends and the plurality of second ends are located on opposite sides of the layer stack;
the plurality of first ends of the first set of vertical structures are connected to a first set of conductive lines;
the plurality of second ends of the second set of vertical structures are connected to a second set of conductive lines; and
the first set of conductive lines and the second set of conductive lines are located on opposite sides of the layer stack.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first set of vertical structures includes a first set of the NAND memory strings and the second set of vertical structures includes a second set of the NAND memory strings different from the first set of the NAND memory strings.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first set of vertical structures include a plurality of NAND memory strings and the second set of vertical structures include a plurality of conductive contacts.

### Claim 4 (depends on 1)

The memory device of claim 1,
wherein the first set of conductive lines are vertically distanced from the plurality of first ends of the first set of vertical structures and the second set of vertical structures; and
wherein the second set of conductive lines are vertically distanced from the plurality of second ends of the first set of vertical structures and the second set of vertical structures.

### Claim 5 (depends on 1)

The memory device of claim 1, further comprising:
one or more peripheral devices formed on a substrate; and
one or more first interconnect layers disposed over the one or more peripheral devices, wherein the one or more first interconnect layers are connected to the one or more peripheral devices and the first set of conductive lines.

### Claim 6 (depends on 5)

The memory device of claim 5, further comprising:
a semiconductor layer disposed over the one or more first interconnect layers.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the plurality of first ends of the first set of vertical structures comprise an epitaxially grown material.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the plurality of second ends of the second set of vertical structures comprise a top conductive material or a conductive core.

### Claim 9 (depends on 1)

The memory device of claim 1, further comprising:
one or more peripheral devices formed on a substrate; and
one or more first interconnect layers disposed over the one or more peripheral devices, wherein the one or more first interconnect layers are connected to the one or more peripheral devices and the first set of conductive lines.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the first set of conductive lines is disposed over the one or more first interconnect layers.

### Claim 11 (depends on 9)

The memory device of claim 9, wherein the first set of conductive lines is disposed over the substrate.

### Claim 12

A memory device, comprising:
a semiconductor layer;
a layer stack having alternating conductor and insulator layers disposed on the semiconductor layer;
a plurality of NAND memory strings extending vertically through the layer stack; and
a first set of conductive lines and a second set of conductive lines located on opposite sides of the layer stack, wherein
first ends of the plurality of NAND memory strings are connected to the first set of conductive lines by one or more conductive vias, the one or more conductive vias extending through the semiconductor layer; and
the conductor layers of the layer stack are connected to the second set of conductive lines.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the plurality of NAND memory strings each comprises:
a memory layer;
a channel layer; and
a core insulator material.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the first ends of the plurality of NAND memory strings comprise an epitaxially grown material.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the epitaxially grown material comprises silicon.

### Claim 16 (depends on 12)

The memory device of claim 12, wherein the second ends of the plurality of NAND memory strings comprise a top conductive material.

### Claim 17 (depends on 16)

The memory device of claim 16, the top conductive material comprises doped polysilicon.

### Claim 18 (depends on 12)

The memory device of claim 12, the conductor layers comprise word lines of the memory device.

### Claim 19 (depends on 12)

The memory device of claim 12, the first set of conductive lines comprise bit lines of the memory device.

### Claim 20 (depends on 12)

The memory device of claim 12, further comprising:
one or more peripheral devices formed on a substrate; and
one or more first interconnect layers disposed over the one or more peripheral devices, wherein the one or more first interconnect layers are connected to the one or more peripheral devices and the first set of conductive lines.