# US 11,443,805 B2 · Electronic device and method of operating memory cell in the electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,805 B2 - Document ID: US11443805B2 - Status: Granted - Kind: B2 - Application number: 17/131,456 - Filed: 2020-12-22 - Published: 2021-04-15 - Granted: 2022-09-13 - Earliest claimed: 2019-06-04 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sang Hyun Ban; Beom Seok Lee; Woo Tae Lee; Tae Hoon Kim; Hwan Jun Zang; Hye Jung Choi - Web page: https://patentgrep.com/patent/US11443805B2 ## CPC - G11C 13/0097: {Erasing, e.g. resetting, circuits or methods} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2013/005: {Read using potential difference applied between cell electrodes} - G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning} - G11C 2013/009: {Write using potential difference applied between cell electrodes} - G11C 2213/15: Current-voltage curve - G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An electronic device includes a semiconductor memory. The semiconductor memory includes word lines, bit lines intersecting the word lines, and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cells. In a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells. ## Claims ### Claim 1 An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: word lines; bit lines intersecting the word lines; and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cell, wherein, in a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells without another voltage applying operation. ### Claim 2 (depends on 1) The electronic device of claim 1, wherein the sub-threshold voltage is set in a unit of a memory chip. ### Claim 3 (depends on 1) The electronic device of claim 1, wherein the sub-threshold voltage is set in a unit of a memory bank. ### Claim 4 (depends on 1) The electronic device of claim 1, wherein the sub-threshold voltage is set in a unit of a MAT. ### Claim 5 (depends on 1) The electronic device of claim 1, wherein a ratio of the sub-threshold voltage and a highest threshold voltage is greater than 0.7. ### Claim 6 (depends on 1) The electronic device of claim 1, wherein a ratio of the lowest threshold voltage and a highest threshold voltage is greater than 0.737. ### Claim 7 (depends on 1) The electronic device of claim 1, wherein a highest threshold voltage is smaller than 1.36 times of the lowest threshold voltage. ### Claim 8 (depends on 1) The electronic device of claim 1, wherein the sub-threshold voltage is greater than 0.7 times of the lowest threshold voltage and is smaller than 0.95 times of the lowest threshold voltage. ### Claim 9 (depends on 1) The electronic device of claim 1, wherein the memory cell maintains a turn-off state during the reset operation. ### Claim 10 (depends on 1) The electronic device of claim 1, wherein the memory cell is programmed to the high-resistance amorphous state or a low-resistance amorphous state, and wherein, in a read operation, a read voltage is applied to the memory cell, and the read voltage has a value between a threshold voltage of the memory cell programmed to the high-resistance amorphous state and a threshold voltage of the memory cell programmed to the low-resistance amorphous state. ### Claim 11 A method for operating an electronic device including memory cells, the method comprising: performing a reset operation of programming a selected memory cell among the memory cells to a high-resistance amorphous state by applying a sub-threshold voltage to the selected memory cell without another voltage applying operation, wherein the sub-threshold voltage is lower than a lowest threshold voltage among threshold voltages of the memory cells, and wherein each of the memory cells includes a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cell. ### Claim 12 (depends on 11) The method of claim 11, wherein the sub-threshold voltage is set in a unit of a memory chip. ### Claim 13 (depends on 11) The method of claim 11, wherein the sub-threshold voltage is set in a unit of a memory bank. ### Claim 14 (depends on 11) The method of claim 11, wherein the sub-threshold voltage is set in a unit of a MAT. ### Claim 15 (depends on 11) The method of claim 11, wherein the sub-threshold voltage is greater than 0.7 times of the lowest threshold voltage and is smaller than 0.95 times of the lowest threshold voltage. ### Claim 16 A method of manufacturing an electronic device including memory cells, the method comprising: forming memory cells, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cell; measuring threshold voltages of the memory cells; and setting a sub-threshold voltage to be lower than a lowest threshold voltage among the threshold voltages of the memory cells, wherein a reset operation of programming a selected memory cell among the memory cells to a high-resistance amorphous state is performed by applying the sub-threshold voltage to the selected memory cell without another voltage applying operation. ### Claim 17 (depends on 16) The method of claim 16, wherein the sub-threshold voltage is set in a unit of a memory chip. ### Claim 18 (depends on 16) The method of claim 16, wherein the sub-threshold voltage is set in a unit of a memory bank. ### Claim 19 (depends on 16) The method of claim 16, wherein the sub-threshold voltage is set in a unit of a MAT. ### Claim 20 (depends on 16) The method of claim 16, wherein the sub-threshold voltage is greater than 0.7 times of the lowest threshold voltage and is smaller than 0.95 times of the lowest threshold voltage.