# US 11,443,804 B2 · Sensing techniques for resistive memory

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- Number: US 11,443,804 B2
- Document ID: US11443804B2
- Status: Granted
- Kind: B2
- Application number: 17/122,031
- Filed: 2020-12-15
- Published: 2022-06-16
- Granted: 2022-09-13
- Earliest claimed: 2020-12-15
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Cyrille Nicolas Dray; El Mehdi Boujamaa
- Web page: https://patentgrep.com/patent/US11443804B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 7/067: {Single-ended amplifiers}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 29/026: {in sense amplifiers}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 11/419: Read-write [R-W] circuits
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Various implementations described herein are related to a device having a sense amplifier that provides output data based on sensing a difference between input signals. The device may have a tracking circuit that tracks a resistive state of a bitcell and provides an input signal to the sense amplifier based on the tracked resistive state of the bitcell. The device may have a bitcell circuit that senses a data value associated with the resistive state of the bitcell and provides another input signal to the sense amplifier based on the sensed data value of the bitcell.

## Claims

### Claim 1

A device comprising:
a sense amplifier that provides output data based on sensing a difference between input signals;
a tracking circuit that tracks a resistive state of a bitcell and provides an input signal to the sense amplifier based on the tracked resistive state of the bitcell, the tracking circuit having a first resistive bitcell coupled in series with a first resistor to an inverting input of the sense amplifier; and
a bitcell circuit that senses a data value associated with the resistive state of the bitcell and provides another input signal to the sense amplifier based on the sensed data value of the bitcell, the bitcell circuit having the bitcell as a second resistive bitcell coupled in series with a second resistor to a non-inverting input of the sense amplifier.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the input signals refer to a first input signal and a second input signal,
the tracking circuit provides the first input signal to an inverting input of the sense amplifier based on the tracked resistive state of the bitcell, and
the bitcell circuit provides the second input signal to a non-inverting input of the sense amplifier based on the sensed data value of the bitcell.

### Claim 3 (depends on 2)

The device of claim 2, wherein:
the tracking circuit has a first variable resistor coupled to the inverting input of the sense amplifier, and
the bitcell circuit has the bitcell coupled in series with a second variable resistor to the non-inverting input of the sense amplifier.

### Claim 4 (depends on 3)

The device of claim 3, wherein:
the bitcell refers to a magneto-resistive bitcell having a programmable resistive state set to a low resistive value or a high resistive value.

### Claim 5 (depends on 1)

The device of claim 1, wherein:
the first resistive bitcell refers to a first magneto-resistive bitcell having a constant resistive state set to a low resistive value, and
the second resistive bitcell refers to a second magneto-resistive bitcell having a programmable resistive state set to a low resistive value or a high resistive value.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first resistor refers to a first variable resistor, and wherein the second resistor refers to a second variable resistor.

### Claim 7 (depends on 1)

The device of claim 1, wherein:
the tracking circuit has a first access passgate coupled in series between the first resistive bitcell and the inverting input of the sense amplifier, and
the first access passgate passes the first input signal to the inverting input of the sense amplifier when activated with a first wordline selection signal.

### Claim 8 (depends on 1)

The device of claim 1, wherein:
the bitcell circuit has a second access passgate coupled in series between the second resistive bitcell and the non-inverting input of the sense amplifier, and
the second access passgate passes the second input signal to the non-inverting input of the sense amplifier when activated with a second wordline selection signal.

### Claim 9 (depends on 1)

The device of claim 1, wherein the sense amplifier refers to an operational amplifier that operates as a differential sensing amplifier that is configured to sense the difference between the input signals and provide the output data as a data output signal based on sensing the difference between the input signals.

### Claim 10

A device comprising:
sense amplifier circuitry having an array of sense amplifiers that provides multi-bit output data based on sensing a difference between multiple input signals,
wherein each sense amplifier in the array of sense amplifiers includes:
tracking circuitry that tracks a resistive state of a memory cell and provides a first input signal of the multiple input signals to each sense amplifier based on the tracked resistive state of the memory cell, the tracking circuitry for each sense amplifier having a first resistive bitcell coupled in series with a first resistor to an inverting input of each sense amplifier; and
memory circuitry that senses a data value associated with the resistive state of the memory cell and provides a second input signal of the multiple input signals to each sense amplifier based on the sensed data value of the memory cell, the memory circuitry for each sense amplifier having the memory cell as a second resistive bitcell coupled in series with a second resistor to a non-inverting input of each sense amplifier.

### Claim 11 (depends on 10)

The device of claim 10, wherein:
the first resistive bitcell for each sense amplifier refers to a first magneto-resistive bitcell having a constant resistive state set to a low resistive value, and
the second resistive bitcell for each sense amplifier refers to a second magneto-resistive bitcell having a programmable resistive state set to a low resistive value or a high resistive value.

### Claim 12 (depends on 10)

The device of claim 10, wherein:
the first resistor for each sense amplifier is coupled together with the other first resistors of each other sense amplifier,
the first resistor for each sense amplifier refers to a first variable resistor that is globally trimmable together with the other first variable resistors of each other sense amplifier,
the second resistor for each sense amplifier is coupled together with the other second resistors of each other sense amplifier, and
the second resistor for each sense amplifier refers to a second variable resistor that is globally trimmable together with the other second variable resistors of each other sense amplifier.

### Claim 13 (depends on 10)

The device of claim 10, wherein:
the tracking circuitry for each sense amplifier has a first access passgate coupled in series between the first resistive bitcell and the inverting input of each sense amplifier,
the first access passgate passes the first input signal to the inverting input of each sense amplifier when activated with a first wordline selection signal,
the bitcell circuitry for each sense amplifier has a second access passgate coupled in series between the second resistive bitcell and the non-inverting input of each sense amplifier, and
the second access passgate passes the second input signal to the non-inverting input of each sense amplifier when activated with a second wordline selection signal.

### Claim 14 (depends on 10)

The device of claim 10, wherein:
the tracking circuitry for each sense amplifier has a first variable resistor coupled to an inverting input of each sense amplifier,
the bitcell circuitry for each sense amplifier has the bitcell coupled in series with a second variable resistor to the non-inverting input of the sense amplifier, and
the bitcell refers to a magneto-resistive bitcell having a programmable resistive state set to a low resistive value or a high resistive value.

### Claim 15 (depends on 14)

The device of claim 14, wherein:
the first variable resistor for each sense amplifier is globally trimmable together with the other first variable resistors of each other sense amplifier, and
the second variable resistor for each sense amplifier is globally trimmable together with the other second variable resistors of each other sense amplifier.

### Claim 16

A method comprising:
fabricating an array of sense amplifiers that provides multi-bit output data signals based on sensing a difference between multiple input signals;
fabricating tracking circuitry for the sense amplifiers that tracks resistive states of bitcells and provides first input signals to the sense amplifiers based on the tracked resistive states of the bitcells, the tracking circuitry for each sense amplifier having a first resistive bitcell coupled in series with a first resistor to an inverting input of each sense amplifier; and
fabricating memory circuitry for the sense amplifiers that senses stored data values associated with the resistive states of the bitcells and provides second input signals to the sense amplifiers based on the sensed data values of the bitcells, the memory circuitry for each sense amplifier having the memory cell as a second resistive bitcell coupled in series with a second resistor to a non-inverting input of each sense amplifier.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the tracking circuitry for the sense amplifiers includes the first resistors as first variable resistors that are globally trimmable together with the other first variable resistors of each other sense amplifier in the array of sense amplifiers, and
the memory circuitry for the sense amplifiers includes the second resistors as second variable resistors that are globally trimmable together with the other second variable resistors of each other sense amplifier in the array of sense amplifiers.

### Claim 18 (depends on 16)

The method of claim 16, wherein:
the bitcells refer to magneto-resistive bitcells having a selectively programmable resistive state set to a low resistive value or a high resistive value.