# US 11,443,803 B2 · Memory device and method thereof

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- Number: US 11,443,803 B2
- Document ID: US11443803B2
- Status: Granted
- Kind: B2
- Application number: 17/095,664
- Filed: 2020-11-11
- Published: 2021-03-04
- Granted: 2022-09-13
- Earliest claimed: 2018-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jau-Yi Wu; Win-San Khwa; Jin Cai; Yu-Sheng Chen
- Web page: https://patentgrep.com/patent/US11443803B2

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/0038: {Power supply circuits}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0052: {Read process characterized by the shape, e.g. form, length, amplitude of the read pulse}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.

## Claims

### Claim 1

A method, comprising:
applying a first signal to a plurality of memory cells in a memory device, to adjust resistance values of the plurality of memory cells;
after applying the first signal, applying a second signal to the plurality of memory cells other than a first memory cell in the plurality of memory cells, to further adjust the resistance values of the plurality of memory cells other than the first memory cell;
when a resistance value of the first memory cell does not reach a first predetermined resistance value, calculating a first difference between the resistance value of the first memory cell and the first predetermined resistance value; and
adjusting the resistance value of the first memory cell based on the first difference.

### Claim 2 (depends on 1)

The method of claim 1, wherein
a voltage level of the second signal is greater than a voltage level of the first signal,
applying the first signal is performed to decrease the resistance values of the plurality of memory cells, and
applying the second signal is performed to further decrease the resistance values of the plurality of memory cells other than the first memory cell.

### Claim 3 (depends on 1)

The method of claim 1, wherein
applying the first signal is performed to increase the resistance values of the plurality of memory cells, and
applying the second signal is performed to further increase the resistance values of the plurality of memory cells other than the first memory cell.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
after applying the first signal and the second signal,
when a resistance value of a second memory cell in the plurality of memory cells does not reach a second predetermined resistance value,
calculating a second difference between the resistance value of the second memory cell and the second predetermined resistance value, and
based on the first difference and the second difference, applying corresponding signals to the first memory cell and/or the second memory cell, to further adjust the resistance values of the first memory cell and/or the second memory cell.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
after applying the first signal, before applying the second signal, performing no reading operation of retrieving the resistance value of the first memory cell for verification.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first signal and the second signal are pulse signals, and a voltage level of the second signal is greater than a voltage level of the first signal.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
verifying levels of threshold voltages of the plurality of memory cells, wherein applying the first signal and applying the second signal are performed according to the verified levels of threshold voltages of the plurality of memory cells.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
generating programming signals based on the threshold voltages; and
extracting the first signal and the second signal from the programming signals.

### Claim 9

A method, comprising:
writing first memory cells of a plurality of memory cells with a first group of pulses, wherein the first group of pulses are configured to decrease resistance values of the first memory cells;
writing second memory cells of the plurality of memory cells with a second group of pulses, wherein the second group of pulses are configured to increase resistance values of the second memory cells;
detecting threshold voltages of the plurality of memory cells; and
generating the first group of pulses based on the threshold voltages.

### Claim 10 (depends on 9)

The method of claim 9, wherein writing the first memory cells with the first group of pulses comprises:
writing the first memory cells with a first pulse in the first group of pulses; and
writing at least one memory cell in the first memory cells with a second pulse in the first group of pulses.

### Claim 11 (depends on 10)

The method of claim 10, wherein a voltage level of the first pulse is lower than a voltage level of the second pulse.

### Claim 12 (depends on 10)

The method of claim 10, wherein
writing the first memory cells with the first pulse is performed to decrease resistance values of the first memory cells, and writing the at least one memory cell with the second pulse is performed to further decrease a resistance value of the at least one memory cell.

### Claim 13 (depends on 9)

The method of claim 9, wherein writing the second memory cells with the second group of pulses comprises:
after writing the second memory cells with a first pulse in the second group of pulses, writing at least one memory cell in the second memory cells with a second pulse in the second group of pulses.

### Claim 14 (depends on 9)

The method of claim 9, further comprising:
generating the second group of pulses based on the threshold voltages.

### Claim 15

A memory device, comprising:
a plurality of memory cells;
a write circuit coupled to the plurality of memory cells, wherein the write circuit is configured to write the plurality of memory cells, to adjust resistance values of the plurality of memory cells, and further configured to write at least one first memory cell in the plurality of memory cells to further adjust the resistance value of the at least one first memory cell; and
a pulse counter circuit coupled to the write circuit and configured to adjust the resistance values of the plurality of memory cells based on differences between predetermined resistance values and the resistance values of the plurality of memory cells.

### Claim 16 (depends on 15)

The memory device of claim 15, further comprising:
a read circuit coupled to the plurality of memory cells,
wherein the read circuit is configured to read the plurality of memory cells in order to compare the predetermined resistance values with the resistance values of the plurality of memory cells.

### Claim 17 (depends on 16)

The memory device of claim 16,
wherein the pulse counter circuit is further configured to generate, based on the differences of the predetermined resistance values with the resistance values of the plurality of memory cells, counter signals for adjusting the resistance values of the plurality of memory cells.

### Claim 18 (depends on 17)

The memory device of claim 17, further comprising:
a row selection circuit coupled to word lines that are coupled to the plurality of memory cells, wherein the row selection circuit is configured to select memory cells in the plurality of memory cells, to be written based on the counter signals through corresponding word lines in the word lines; and
a column selection circuit coupled to bit lines that are coupled to the plurality of memory cells, wherein the column selection circuit is configured to select at least one of the bit lines in order to transmit currents in response to the resistance values of the plurality of memory cells.

### Claim 19 (depends on 16)

The memory device of claim 16, wherein the read circuit is configured to distinguish threshold voltages of the plurality of memory cells based on currents flowing through the plurality of memory cells, and
the resistances values of the plurality of memory cells are verified based on the threshold voltages.

### Claim 20 (depends on 15)

The memory device of claim 15, wherein each of the plurality of memory cells comprises:
a resistor comprising a phase-change material, wherein data stored in each of the plurality of memory cells corresponds to a resistance value presented by the resistor; and
a switch coupled to the resistor and configured to be controlled by the write circuit in order to conduct a current flowing through the resistor.