# US 11,443,802 B2 · Adaptive memory management and control circuitry

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,443,802 B2
- Document ID: US11443802B2
- Status: Granted
- Kind: B2
- Application number: 16/924,958
- Filed: 2020-07-09
- Published: 2022-01-13
- Granted: 2022-09-13
- Earliest claimed: 2020-07-09
- Assignees: Numem Inc.
- Applicants: NUMEM Inc.
- Inventors: Eric Hall; Doug Smith; Nicholas T. Hendrickson; Jack Guedj
- Web page: https://patentgrep.com/patent/US11443802B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 11/1653: {Address circuits or decoders}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/1693: {Timing circuits or methods}
- G11C 11/225: {Auxiliary circuits}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2293: {Timing circuits or methods}
- G11C 13/0021: {Auxiliary circuits}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details}
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

## Claims

### Claim 1

Resistive memory comprising:
a resistive memory array; and
an adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with extended test, reliability, performance or power optimizing capabilities, wherein the AMMC is configured with the performance optimizing capabilities to optimize memory speed with reduced memory endurance or to optimize memory endurance with reduced memory speed.

### Claim 2 (depends on 1)

The resistive memory of claim 1, wherein the AMMC is integrated with the resistive memory array.

### Claim 3 (depends on 1)

The resistive memory of claim 1, wherein the AMMC is configured with performance optimizing capabilities and power optimizing capabilities.

### Claim 4 (depends on 1)

The resistive memory of claim 1, further comprising:
a memory mapped interface to map adaptive memory management and control features to a memory mapped region of the resistive memory.

### Claim 5 (depends on 1)

The resistive memory of claim 1, wherein the AMMC includes built-in self test circuitry to test functionality of the resistive memory array that is extended to additional testing functions.

### Claim 6 (depends on 1)

The resistive memory of claim 1, wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive RAM (RRAM), phase-change RAM (PCRAM), or Ferroelectric RAM (FeRAM).

### Claim 7

A memory subsystem comprising:
a smart compute memory circuitry;
a resistive memory array coupled to the smart compute memory circuitry; and
an Adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with extended test and performance optimizing capabilities, wherein the smart compute memory circuitry comprises an integrated processor with power-management control and memory management control.

### Claim 8 (depends on 7)

The memory subsystem of claim 7, wherein the smart compute memory circuitry comprises an integrated processor with power-management control and memory management control to augment memory management and control of the AMMC.

### Claim 9 (depends on 7)

The memory subsystem of claim 7, wherein the integrated processor is configured with programmable memory management and control to optimize parameters with different modes including a first mode to manipulate data to encrypt or decrypt the data as needed, a second mode for writing or reading at different speeds to optimize power and performance over a temperature range, a third mode to generate a custom sequence of read and write operations, and a fourth mode to generate a conditional read or write operation based on output from a logic function.

### Claim 10 (depends on 7)

The memory subsystem of claim 7, wherein the AMMC comprises an integrated temperature control circuitry to sense temperature, wherein the AMMC is configured to adaptively change power and performance over a temperature range based on sensed temperature data of the resistive memory array using the integrated temperature control circuitry.

### Claim 11 (depends on 7)

The memory subsystem of claim 7, wherein the AMMC includes built-in self test (BIST) circuitry to test functionality of the resistive memory array.

### Claim 12 (depends on 9)

The memory subsystem of claim 9, wherein the integrated processor is configured to execute test code for the BIST circuitry with the test code being stored in a first region of the resistive memory array while a second region of the resistive memory array is being tested.

### Claim 13 (depends on 11)

The memory subsystem of claim 11, wherein the AMMC to adaptively enable optimization of power by reading and writing to a first region of the resistive memory array while operating a second region of the resistive memory array in a low power mode.

### Claim 14 (depends on 7)

The computing system of claim 7, wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive RAM (RRAM), phase-change RAM (PCRAM), or Ferroelectric RAM (FeRAM).