# US 11,443,800 B2 · Semiconductor memory apparatus for preventing disturbance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,800 B2 - Document ID: US11443800B2 - Status: Granted - Kind: B2 - Application number: 17/084,366 - Filed: 2020-10-29 - Published: 2021-02-18 - Granted: 2022-09-13 - Earliest claimed: 2018-03-27 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jin Su Park - Web page: https://patentgrep.com/patent/US11443800B2 ## CPC - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/003: {Cell access} - G11C 13/0038: {Power supply circuits} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 7/02: with means for avoiding parasitic signals - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line. ## Claims ### Claim 1 A semiconductor memory apparatus comprising: a plurality of global bit lines; a plurality of bit line groups each including a plurality of bit lines coupled with the plurality of global bit lines, respectively; and a bit line control circuit configured to select one of the plurality of bit line groups based on a bit line select signal and configured to apply at least two of a selected bit line bias voltage, a first unselected bit line bias voltage, a second unselected bit line bias voltage, and a third unselected bit line bias voltage to the plurality of global bit lines. ### Claim 2 (depends on 1) The semiconductor memory apparatus according to claim 1, wherein the first unselected bit line bias voltage is lower than the third unselected bit line bias voltage, wherein the third unselected bit line bias voltage is lower than the second unselected bit line bias voltage, and wherein the second unselected bit line bias voltage is lower than the selected bit line bias voltage. ### Claim 3 (depends on 2) The semiconductor memory apparatus according to claim 2, wherein the bit line control circuit applies the selected bit line bias voltage to a global bit line coupled with a selected bit line of a bit line group selected from the plurality of bit line groups based on the bit line select signal, wherein the bit line control circuit applies the first unselected bit line bias voltage to a global bit line coupled with a remaining bit line of the selected bit line group, and wherein the plurality of bit lines of an unselected bit line group of the plurality of bit line groups are driven with the second unselected bit line bias voltage. ### Claim 4 (depends on 2) The semiconductor memory apparatus according to claim 2, wherein the bit line control circuit applies the selected bit line bias voltage to a global bit line coupled with a selected bit line of a bit line group selected from the plurality of bit line groups based on the bit line select signal, wherein the bit line control circuit applies the first unselected bit line bias voltage to a global bit line coupled with a bit line adjacent to the selected bit line in the selected bit line group, and wherein the bit line control circuit applies at least one of the second unselected bit line bias voltage and the third unselected bit line bias voltage to a global bit line coupled with a bit line not adjacent to the selected bit line in the selected bit line group. ### Claim 5 (depends on 2) The semiconductor memory apparatus according to claim 2, further comprising: an unselected voltage supply circuit configured to apply the second unselected bit line bias voltage to the plurality of bit lines of an unselected bit line group among the plurality of bit line groups. ### Claim 6 (depends on 2) The semiconductor memory apparatus according to claim 2, wherein the plurality of global bit lines comprises first to eighth global bit lines, the plurality of bit lines comprises first to fourth bit lines, the plurality of bit line groups comprises first to third bit line groups, and the bit line control circuit generates first to third group select signals based on the bit line select signal, and wherein the semiconductor memory apparatus further comprises: a first group switch configured to couple the first to fourth bit lines of the first bit line group with the first to fourth global bit lines, respectively, based on the first group select signal; a second group switch configured to couple the first to fourth bit lines of the second bit line group with the fifth to eighth global bit lines, respectively, based on the second group select signal, the first bit line of the second bit line group being adjacent to the fourth bit line of the first bit line group; and a third group switch configured to couple the first to fourth bit lines of the third bit line group with the first to fourth global bit lines, respectively, based on the third group select signal, the first bit line of the third bit line group being adjacent to the fourth bit line of the second bit line group. ### Claim 7 (depends on 6) The semiconductor memory apparatus according to claim 6, wherein, when the second bit line or the third bit line of the second bit line group is selected based on the bit line select signal, the bit line control circuit enables the second group select signal and disables the first and third group select signals, and wherein the bit line control circuit applies the selected bit line bias voltage to a global bit line coupled with a selected bit line, applies the first unselected bit line bias voltage to a global bit line coupled with a bit line adjacent to the selected bit line, and applies at least one of the second unselected bit line bias voltage and the third unselected bit line bias voltage to a global bit line coupled with a bit line not adjacent to the selected bit line. ### Claim 8 (depends on 7) The semiconductor memory apparatus according to claim 7, further comprising: an unselected voltage supply circuit configured to apply the second unselected bit line bias voltage to the first to fourth bit lines of the first to third bit line groups based on the first to third group select signals. ### Claim 9 (depends on 6) The semiconductor memory apparatus according to claim 6, wherein, when the first bit line of the second bit line group is selected based on the bit line select signal, the bit line control circuit enables the first and second group select signals and disables the third group select signal, and wherein the bit line control circuit applies the selected bit line bias voltage to the fifth global bit line, applies the first unselected bit line bias voltage to the fourth and sixth global bit lines, and applies at least one of the second unselected bit line bias voltage and the third unselected bit line bias voltage to the first to third global bit lines and the seventh and eighth global bit lines. ### Claim 10 (depends on 6) The semiconductor memory apparatus according to claim 6, wherein, when the fourth bit line of the second bit line group is selected based on the bit line select signal, the bit line control circuit enables the second and third group select signals and disables the first group select signal, and wherein the bit line control circuit applies the selected bit line bias voltage to the eighth global bit line, applies the first unselected bit line bias voltage to the first and seventh global bit lines, and applies at least one of the second unselected bit line bias voltage and the third unselected bit line bias voltage to the second to fourth global bit lines and the fifth and sixth global bit lines. ### Claim 11 A semiconductor memory apparatus comprising: a bit line control circuit configured to apply a selected bit line bias voltage to a selected bit line coupled with a target memory cell and configured to apply a bit line voltage, having a voltage level between a first unselected bit line bias voltage and a second unselected bit line bias voltage, which is higher in proportion to a distance from the selected bit line to an unselected bit line to which the bit line voltage is applied. ### Claim 12 (depends on 11) The semiconductor memory apparatus according to claim 11, wherein the first unselected bit line bias voltage is lower than the second unselected bit line bias voltage, and wherein the second unselected bit line bias voltage is lower than the selected bit line bias voltage.