# US 11,443,796 B2 · Memory device and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,796 B2 - Document ID: US11443796B2 - Status: Granted - Kind: B2 - Application number: 16/972,696 - Filed: 2019-06-13 - Published: 2021-08-19 - Granted: 2022-09-13 - Earliest claimed: 2018-06-22 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Takahiko Ishizu; Toshihiko Saito; Hideki Uochi; Shunpei Yamazaki - Web page: https://patentgrep.com/patent/US11443796B2 ## CPC - G11C 11/403: with charge regeneration common to a multiplicity of memory cells, i.e. external refresh - G11C 11/419: Read-write [R-W] circuits - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups - G11C 11/409: Read-write [R-W] circuits - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - H10B 12/00: Dynamic random access memory [DRAM] devices - H10B 41/70: the floating gate being an electrode shared by two or more components - H10D 30/6756: {Amorphous oxide semiconductors} - H10D 62/405: {Orientations of crystalline planes} - G11C 11/4094: Bit-line management or control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved. ## Claims ### Claim 1 A memory device comprising: a memory cell; a first region; a first word line; a second word line; a first bit line; and a second bit line, wherein the memory cell comprises a first transistor and a second transistor, wherein a semiconductor layer of the first transistor comprises a metal oxide, wherein the first region comprises a plurality of gaps, wherein the first bit line and the second bit line extend in a first direction, wherein the first word line and the second word line extend in a second direction, wherein a gate of the first transistor is electrically connected to the first word line, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the first bit line, wherein one of a source and a drain of the second transistor is electrically connected to the second word line, wherein the other of the source and the drain of the second transistor is electrically connected to the second bit line, wherein the first region comprises a region extending in the first direction, wherein in the region extending in the first direction, each of the plurality of gaps extends in a direction intersecting with the first direction, and wherein an area where a gate electrode and a semiconductor layer of the second transistor overlap with each other is larger than an area where a gate electrode and the semiconductor layer of the first transistor overlap with each other. ### Claim 2 A memory device comprising: a memory cell; a first region; a first word line; a second word line; a first bit line; a second bit line; and a first conductive layer, wherein the memory cell comprises a first transistor and a second transistor, wherein a semiconductor layer of the first transistor comprises a metal oxide, wherein the first region comprises a plurality of gaps, wherein the first bit line and the second bit line extend in a first direction, wherein the first word line and the second word line extend in a second direction, wherein a gate of the first transistor is electrically connected to the first word line, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the first bit line, wherein one of a source and a drain of the second transistor is electrically connected to the second word line, wherein the other of the source and the drain of the second transistor is electrically connected to the second bit line, wherein the first conductive layer comprises a region overlapping with the semiconductor layer of the first transistor and a region overlapping with the one of the source and the drain of the first transistor, wherein the first region comprises a region extending in the first direction, and wherein in the region extending in the first direction, each of the plurality of gaps extends in a direction intersecting with the first direction. ### Claim 3 (depends on 2) The memory device according to claim 2, wherein the first conductive layer comprises a region configured to be a back gate of the first transistor. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein the semiconductor layer contains at least one of In and Zn. ### Claim 5 (depends on 1) The memory device according to claim 1, wherein the first region comprises a region extending in the second direction, and wherein in the region extending in the second direction, each of the plurality of gaps comprises a region extending in a direction intersecting with the second direction. ### Claim 6 (depends on 1) The memory device according to claim 1, wherein the area where the gate electrode and the semiconductor layer of the second transistor overlap with each other is greater than or equal to 1 time and less than or equal to 10 times the area where the gate electrode and the semiconductor layer of the first transistor overlap with each other. ### Claim 7 (depends on 1) An electronic device comprising: the memory device according to claim 1; and at least one of a microphone, a camera, a speaker, an antenna, and a battery. ### Claim 8 (depends on 2) The memory device according to claim 2, wherein the semiconductor layer contains at least one of In and Zn. ### Claim 9 (depends on 2) The memory device according to claim 2, wherein the first region comprises a region extending in the second direction, and wherein in the region extending in the second direction, each of the plurality of gaps comprises a region extending in a direction intersecting with the second direction. ### Claim 10 (depends on 2) The memory device according to claim 2, wherein an area where a gate electrode and a semiconductor layer of the second transistor overlap with each other is larger than an area where a gate electrode and a semiconductor layer of the first transistor overlap with each other. ### Claim 11 (depends on 2) The memory device according to claim 2, wherein the area where the gate electrode and the semiconductor layer of the second transistor overlap with each other is greater than or equal to 1 time and less than or equal to 10 times the area where the gate electrode and the semiconductor layer of the first transistor overlap with each other. ### Claim 12 (depends on 2) An electronic device comprising: the memory device according to claim 2; and at least one of a microphone, a camera, a speaker, an antenna, and a battery.