# US 11,443,793 B2 · Battery life based on inhibited memory refreshes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,793 B2 - Document ID: US11443793B2 - Status: Granted - Kind: B2 - Application number: 17/068,732 - Filed: 2020-10-12 - Published: 2021-02-11 - Granted: 2022-09-13 - Earliest claimed: 2019-06-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Ramkumar Jayaraman; Krishnaprasad H; Kausik Ghosh - Web page: https://patentgrep.com/patent/US11443793B2 ## CPC - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G06F 1/3225: of memory devices - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/3287: by switching off individual functional units in the computer system - G06F 13/1636: {using refresh} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic. ## Claims ### Claim 1 An apparatus comprising: a processor; and a memory controller coupled to the processor, wherein the memory controller is to: identify a command provided to a memory interface; set, based on an identification that the command targets a first range of memory and an identification that the command is of a type for which memory refreshes are employed, a stored value of a register to a predetermined value; determine, based on the stored value of the register being the predetermined value, that the first range of memory is to remain active; and allow, based on the stored value of the register being the predetermined value, the first range of memory to refresh. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the memory controller is to allow propagation of a refresh cycle to allow the first range of memory to refresh. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the memory controller is further to prevent, if the stored value of the register is not the predetermined value, propagation of a refresh cycle to inhibit the first range of memory to refresh. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first range is within a Dynamic Random Access Memory (DRAM) Dual In-Line Memory Module (DIMM). ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the first range is a rank of memory on the DRAM DIMM. ### Claim 6 (depends on 1) The apparatus of claim 1 comprising the memory interface to be communicatively coupled to the memory, wherein the memory controller is to allow the first range of memory to refresh. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the command is a write command. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the stored value is set to an initialized value after removal and replacement of power to the first range of the memory. ### Claim 9 A machine-readable storage media having one or more machine-readable instructions stored thereon that, when executed, cause one or more machines to perform a method comprising: identifying a command provided to a memory interface; setting, based on an identification that the command targets a first range of memory and an identification that the command is of a type for which memory refreshes are employed, a stored value of a register to a predetermined value; determining, based on the stored value of the register being the predetermined value, that the first range of memory that is to remain active; and allowing, based on the stored value of the register being the predetermined value, the first range of memory to refresh. ### Claim 10 (depends on 9) The machine-readable storage media of claim 9, wherein the command is a write command. ### Claim 11 (depends on 9) The machine-readable storage media of claim 9, wherein setting the stored value includes changing the stored value from an initialized value that is based on removing and replacing of power to the first range of the memory. ### Claim 12 (depends on 9) The machine-readable storage media of claim 9, wherein the first range is within a Dynamic Random Access Memory (DRAM) Dual In-Line Memory Module (DIMM). ### Claim 13 (depends on 12) The machine-readable storage media of claim 12, wherein the first range is a rank of memory on the DRAM DIMM. ### Claim 14 A system comprising: a processor; a memory controller coupled to the processor; a Dynamic Random Access Memory (DRAM) Dual In-Line Memory Module (DIMM) coupled to the memory controller via a memory interface; a wireless interface to allow the processor to communicate with another device, wherein the memory controller is to: identify a command provided to the memory interface; set, based on an identification that the command targets a first range of memory and an identification that the command is of a type for which memory refreshes are employed, a stored value of a register to a predetermined value; determine, based on the stored value of the register being the predetermined value, that the first range of memory is to remain active; and allow, based on the stored value of the register being the predetermined value, the first range of memory to refresh, wherein the first range is a rank of memory on the DRAM DIMM. ### Claim 15 (depends on 14) The system of claim 14, wherein the command is a write command. ### Claim 16 (depends on 14) The system of claim 14, wherein the memory controller is to allow propagation of a refresh cycle to allow the first range of memory to refresh. ### Claim 17 (depends on 14) The system of claim 14, wherein the memory controller is further to prevent, if the stored value of the register is not the predetermined value, propagation of a refresh cycle to inhibit the first range of memory to refresh. ### Claim 18 (depends on 14) The system of claim 14, wherein the stored value is set to an initialized value after removal and replacement of power to the first range of the memory.