# US 11,443,792 B1 · Memory cell, memory cell arrangement, and methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,792 B1 - Document ID: US11443792B1 - Status: Granted - Kind: B1 - Application number: 17/400,411 - Filed: 2021-08-12 - Granted: 2022-09-13 - Earliest claimed: 2021-08-12 - Assignees: Ferroelectric Memory GmbH - Applicants: Ferroelectric Memory GmbH - Inventors: Rashid Iqbal; Stefano Sivero; Stefan Ferdinand Müller - Web page: https://patentgrep.com/patent/US11443792B1 ## CPC - G11C 11/223: {using MOS with ferroelectric gate insulating film} - G11C 11/2275: {Writing or programming circuits or methods} - G11C 11/221: {using ferroelectric capacitors} - G11C 11/2255: {Bit-line or column circuits} - G11C 11/2257: {Word-line or row circuits} - G11C 11/2259: {Cell access} - G11C 11/2297: {Power supply circuits} - H10B 53/40: characterised by the peripheral circuit region - H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs} - H10D 64/689: {having ferroelectric layers} - H10B 51/30: characterised by the memory core region - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure. ## Claims ### Claim 1 A memory cell comprising: a source-line node, a bit-line node, a word-line node, and an operating-line node; a field-effect transistor memory structure comprising a field-effect transistor structure and memory element, the memory element comprising a spontaneously polarizable layer, wherein a first source/drain node of the field-effect transistor memory structure is coupled to the source-line node, and wherein a second source/drain node of the field-effect transistor memory structure is coupled to the bit-line node; and an access device, coupled to a gate of the field-effect transistor memory structure, to the word-line node, and to the operating-line node, wherein the access device is configured to control a voltage at the gate of the field-effect transistor memory structure on both a word-line voltage provided at the word-line node and an operating-line voltage provided at the operating-line node, wherein a first electrical conductance state associated with the field-effect transistor memory structure corresponds to a polarization state of the spontaneously polarizable layer of the memory element, and wherein a second electrical conductance state distinct from the first electrical conductance state associated with the field-effect transistor memory structure corresponds to a second polarization state of the spontaneously polarizable layer of the memory element, and wherein a transition from the first electrical conductance state to the second electrical conductance state is associated with a change in a residual polarization of the spontaneously polarizable layer of the memory element. ### Claim 2 (depends on 1) The memory cell according to claim 1, wherein the field-effect transistor memory structure is configured such that a polarization state of the spontaneously polarizable layer of the memory element defines a memory state of the field-effect transistor memory structure. ### Claim 3 (depends on 1) The memory cell according to claim 1, wherein the spontaneously polarizable layer is remanently polarizable. ### Claim 4 (depends on 1) The memory cell according to claim 1, wherein the spontaneously polarizable layer comprises at least one remanent polarizable material. ### Claim 5 (depends on 1) The memory cell according to claim 1, wherein the field-effect transistor memory structure comprises a capacitive memory structure formed by the memory element and a first electrode layer and a second electrode layer, wherein the memory element is in direct physical contact with both the first electrode and the second electrode. ### Claim 6 (depends on 1) The memory cell according to claim 1, wherein the field-effect transistor memory structure comprises a gate electrode layer, a dielectric layer, and a channel region, and wherein at least one of: the memory element is disposed between the gate electrode layer and the channel region of the field-effect transistor memory structure, and/or the memory element is in direct physical contact with both the gate electrode layer and the dielectric layer of the field-effect transistor memory structure, and/or the memory element is disposed between the gate electrode layer and the dielectric layer of the field-effect transistor memory structure. ### Claim 7 (depends on 1) The memory cell according to according to claim 1, wherein the access device comprises an access field-effect transistor structure, wherein a first source/drain node of the access field-effect transistor structure is coupled to the operating-line node, wherein a second source/drain node of the access field-effect transistor structure is coupled to the gate of the field-effect transistor memory structure, and wherein a gate of the access field-effect transistor structure is coupled to the word-line node. ### Claim 8 A memory cell arrangement comprising: a plurality of memory cells, each memory cell of the plurality of memory cells comprising: a source-line node, a bit-line node, a word-line node, and an operating-line node; a field-effect transistor memory structure comprising a field-effect transistor structure and memory element, the memory element comprising a spontaneously polarizable layer, wherein a first source/drain node of the field-effect transistor memory structure is coupled to the source-line node, and wherein a second source/drain node of the field-effect transistor memory structure is coupled to the bit-line node; and an access device, coupled to a gate of the field-effect transistor memory structure, to the word-line node, and to the operating-line node, wherein the access device is configured to control a voltage at the gate of the field-effect transistor memory structure on both a word-line voltage provided at the word-line node and an operating-line voltage provided at the operating-line node; a memory control circuit configured to write a selected memory cell of the plurality of memory cells and to inhibit writing of one or more non-selected memory cells of the plurality of memory cells by a pre-write operation and a write operation subsequent to the pre-write operation. ### Claim 9 (depends on 8) The memory cell arrangement according to claim 8, wherein the memory control circuit is configured to operate the memory cells of the plurality of memory cells. ### Claim 10 (depends on 8) The memory cell arrangement according to claim 8, wherein memory cells of a first subset of the plurality of memory cells share a first word-line electrically connected to respective word-line nodes of the memory cells of the first subset; and/or wherein memory cells of a first subset of the plurality of memory cells share a first source-line electrically connected to respective source-line nodes of the memory cells of the first sub set. ### Claim 11 (depends on 8) The memory cell arrangement according to claim 8, wherein memory cells of a second subset of the plurality of memory cells share a second word-line electrically connected to respective word-line nodes of the memory cells of the second subset; and/or wherein memory cells of a second subset of the plurality of memory cells share a second source-line electrically connected to respective source-line nodes of the memory cells of the second subset. ### Claim 12 (depends on 8) The memory cell arrangement according to claim 8, wherein memory cells of a third subset of the plurality of memory cells share a first bit-line electrically connected to respective bit-line nodes of the memory cells of the third subset; and/or wherein memory cells of a third subset of the plurality of memory cells share a first operating-line electrically connected to respective operating-line nodes of the memory cells of the third subset. ### Claim 13 (depends on 8) The memory cell arrangement according to claim 8, wherein memory cells of a fourth subset of the plurality of memory cells share a second bit-line electrically connected to respective bit-line nodes of the memory cells of the fourth subset; and/or wherein memory cells of a fourth subset of the plurality of memory cells share a second operating-line electrically connected to respective operating-line nodes of the memory cells of the fourth subset. ### Claim 14 (depends on 8) The memory cell arrangement according to claim 8, wherein memory cells of a first subset of the plurality of memory cells share a first word-line electrically connected to respective word-line nodes of the memory cells of the first subset, and wherein memory cells of a second subset of the plurality of memory cells share a second word-line electrically connected to respective word-line nodes of the memory cells of the second subset; and wherein memory cells of the first subset of the plurality of memory cells and memory cells of the second subset of the plurality of memory cells share a common source-line electrically connected to respective source-line nodes of the memory cells of the first subset and of the second subset. ### Claim 15 (depends on 8) The memory cell arrangement according to claim 8, wherein memory cells of a third subset of the plurality of memory cells share a first operating-line electrically connected to respective operating-line nodes of the memory cells of the third subset, and wherein memory cells of a fourth subset of the plurality of memory cells share a second operating-line electrically connected to respective operating-line nodes of the memory cells of the fourth subset; and wherein memory cells of the third subset of the plurality of memory cells and memory cells of the fourth subset of the plurality of memory cells share a common bit-line electrically connected to respective bit-line nodes of the memory cells of the third subset and of the fourth sub set. ### Claim 16 (depends on 8) The memory cell arrangement according to claim 8, wherein an active bit-line and an active source-line correspond to the selected memory cell, and wherein one or more passive bit-lines and one or more passive source-lines correspond to memory cells of one or more non-selected memory cells, and wherein at least one of: the active source-line and at least one of the one or more passive source-lines are configured as a shared source-line, and/or the active bit-line and at least one of the one or more passive bit-lines are configured as a shared bit-line. ### Claim 17 (depends on 8) The memory cell arrangement according to claim 8, wherein the pre-write operation comprises a pre-program operation, the pre-program operation comprising: providing a first supply voltage level at the active word-line and the one or more passive word-lines; and providing a second supply voltage level at the active operating-line, the one or more passive operating-lines, the active bit-line, the one or more passive bit-lines, the active source-line, and the one or more passive source-lines. ### Claim 18 (depends on 8) The memory cell arrangement according to claim 8, wherein the write operation comprises a program operation, the program operation comprising: providing a first supply voltage level at the active word-line and the active operating-line; and providing a second supply voltage level or an inhibit voltage at each of the one or more passive operating-lines, the active source-line, the one or more passive source-lines, the active bit-line, and the one or more passive bit-lines. ### Claim 19 (depends on 8) The memory cell arrangement according to claim 8, wherein the pre-write operation comprises a pre-erase operation, the pre-erase operation comprising: providing a write voltage at the active word-line, the one or more passive word-lines; the active operating-line, the one or more passive operating-lines, the active bit-line, the one or more passive bit-lines, the active source-line, and the one or more passive source-lines. ### Claim 20 (depends on 8) The memory cell arrangement according to claim 8, wherein the write operation comprises an erase operation, the erase operation comprising: providing a first supply voltage level at the active word-line, the active bit-line, the one or more passive bit-lines, the active source-line, and the one or more passive source-lines; and providing a first supply voltage level or an inhibit voltage at the one or more passive operating lines; and providing a second supply voltage level at the one or more passive word-lines, and the active operating line. ### Claim 21 A method for writing a selected memory cell of a memory cell arrangement, the memory cell arrangement comprising: a plurality of memory cells, each memory cell of the plurality of memory cells comprising: a field-effect transistor memory structure connecting a source-line node and a bit-line node of the memory cell with one another, and an access field-effect transistor structure coupled to the field-effect transistor memory structure to control a voltage at a gate of the field-effect transistor memory structure as a function of both a word-line voltage provided to the access field-effect transistor structure via a word-line node of the memory cell and an operating-line voltage provided to the access field-effect transistor structure via an operating-line node of the memory cell; the method comprising: writing the selected memory cell by pre-charge operation and a subsequent write operation corresponding to the pre-charge operation, wherein a respective gate of one or more of the field-effect transistor memory structures of the plurality of memory cells is pre-charged to a predefined voltage level by the pre-charge operation, and wherein the selected memory cell of a memory cell arrangement is written by the subsequent write operation and wherein a writing of one or more non-selected memory cells of the memory cell arrangement is inhibited during the subsequent write operation. ### Claim 22 (depends on 21) The method of claim 21; wherein writing the selected memory cell is based on three or less distinct supply voltage levels. ### Claim 23 A memory cell arrangement comprising: a plurality of memory cells, each memory cell of the plurality of memory cells comprising: a source-line node, a bit-line node, a word-line node, and an operating-line node; a field-effect transistor memory structure comprising a field-effect transistor structure and memory element, the memory element comprising a spontaneously polarizable layer, wherein a first source/drain node of the field-effect transistor memory structure is coupled to the source-line node, and wherein a second source/drain node of the field-effect transistor memory structure is coupled to the bit-line node; and an access device, coupled to a gate of the field-effect transistor memory structure, to the word-line node, and to the operating-line node, wherein the access device is configured to control a voltage at the gate of the field-effect transistor memory structure on both a word-line voltage provided at the word-line node and an operating-line voltage provided at the operating-line node; and wherein memory cells of a subset of the plurality of memory cells share at least one of: a word-line electrically connected to respective word-line nodes of the memory cells of the subset, a source-line electrically connected to respective source-line nodes of the memory cells of the subset, a bit-line electrically connected to respective bit-line nodes of the memory cells of the subset, and/or an operating-line electrically connected to respective operating-line nodes of the memory cells of the subset. ### Claim 24 (depends on 23) The memory cell arrangement according to claim 23, wherein memory cells of a subset of the plurality of memory cells share a word-line electrically connected to respective word-line nodes of the memory cells of the subset and a source-line electrically connected to respective source-line nodes of the memory cells of the sub set. ### Claim 25 (depends on 24) The memory cell arrangement according to claim 24, wherein memory cells of another subset of the plurality of memory cells share a bit-line electrically connected to respective bit-line nodes of the memory cells of the other subset and an operating-line electrically connected to respective operating-line nodes of the memory cells of the other subset.