# US 11,443,789 B1 · Memory device

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- Number: US 11,443,789 B1
- Document ID: US11443789B1
- Status: Granted
- Kind: B1
- Application number: 17/239,710
- Filed: 2021-04-26
- Published: 2022-09-22
- Granted: 2022-09-13
- Earliest claimed: 2021-03-16
- Assignees: Jiangsu Advanced Memory Technology Co., Ltd.; Siloam Holdings Co., Ltd.
- Applicants: Jiangsu Advanced Memory Technology Co., Ltd.; Siloam Holdings Co., Ltd.
- Inventors: Jui-Jen Wu; Toshio Sunaga; Hsiu-Chun Tsai
- Web page: https://patentgrep.com/patent/US11443789B1

## CPC

- G11C 8/10: Decoders
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.

## Claims

### Claim 1

A memory device, comprising:
a memory group, comprising a plurality of memory banks; and
a control circuit, coupled to the memory group, wherein the control circuit comprises:
a tri-state logic enable circuit, configured to temporarily store a plurality of temporarily stored address signals, to output the plurality of temporarily stored address signals according to a synchronization signal, to decode the plurality of temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the plurality of memory banks; the tri-state logic enable circuit comprises a first sequence circuit, configured to generate a plurality of indicator signals according to the synchronization signal and a read signal, the first sequence circuit comprises:
a first flip flop sequence, comprising a plurality of D flip flops, wherein a first D flip flop of the plurality of D flip flops comprises:
an output terminal, configured to output a first indicator signal of the plurality of indicator signals;
a first input terminal, configured to receive a second indicator signal of the plurality of indicator signals output by a second D flip flop of the plurality of D flip flops or a third indicator signal of the plurality of indicator signals output by a third D flip flop of the plurality of D flip flops, wherein the first D flip flop is connected in serious between the second flip flop and the third flip flop;
a second input terminal, configured to receive one of the read signal and the synchronization signal; and
a third input terminal, configured to receive a preset signal; and
an address decoding circuit, configured to decode the plurality of temporarily stored address signals to drive the one of the plurality of memory banks.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the tri-state logic enable circuit outputs the plurality of temporarily stored address signals with a first in first out method.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the tri-state logic enable circuit further comprises:
a second sequence circuit, configured to store and output the plurality of temporarily stored address signals according to the plurality of indicator signals, the synchronization signal, and the read signal, wherein the second sequence circuit comprises:
a tri-state logic enable decoding circuit, configured to generate the enable signal according to the plurality of temporarily stored address signals.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein when the first sequence circuit and the second sequence circuit receive the read signal, the second sequence circuit stores the plurality of temporarily stored address signals; wherein when the first sequence circuit and the second sequence circuit receive the synchronization signal, the second sequence circuit outputs the plurality of temporarily stored address signals.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the second input terminal of the first D flip flop is connected to an OR gate, wherein the OR gate comprises:
a first input terminal, configured to receive the synchronization signal;
a second input terminal, configured to receive the read signal; and
an output terminal, configured to output the synchronization signal or the read signal to the second input terminal of the first D flip flop.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first input terminal of the first D flip flop is connected to a selector, the selector comprises:
a control terminal, configured to receive a select signal;
a first input terminal, configured to receive the second indicator signal; and
a second input terminal, configured to receive the third indicator signal.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first sequence circuit further comprises:
a NAND gate circuit, comprises:
a first input terminal, configured to receive the synchronization signal;
a second input terminal, configured to receive the read signal; and
an output terminal, configured to output the select signal.

### Claim 8 (depends on 3)

The memory device of claim 3, wherein the second sequence circuit further comprises a plurality of flip flop sequences, wherein a first flip flop sequence of the plurality of flip flop sequences comprises:
a plurality of D flip flops, wherein a first D flip flop of the plurality of D flip flops comprises:
an output terminal, configured to output a first temporarily stored address signal of the plurality of temporarily stored address signals;
a first input terminal, configured to receive one of a plurality of input address signals;
a second input terminal, configured to receive a second temporarily stored address signal of the plurality of temporarily stored address signals output by a second D flip flop of the plurality of D flip flops; and
a third input terminal, configured to receive the synchronization signal.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the first input terminal is configured to be connected to an AND gate, wherein the AND gate comprises:
a first input terminal, configured to receive one of the plurality of indicator signals;
a second input terminal, configured to receive the one of the plurality of input address signals; and
an output terminal, configured to output the one of the plurality of input address signals.