# US 11,443,785 B2 · Memory device for generating data strobe signal based on pulse amplitude modulation, memory controller, and memory system including the same

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- Number: US 11,443,785 B2
- Document ID: US11443785B2
- Status: Granted
- Kind: B2
- Application number: 17/344,610
- Filed: 2021-06-10
- Published: 2022-03-03
- Granted: 2022-09-13
- Earliest claimed: 2020-09-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sucheol Lee; Jaewoo Park; Younghoon Son; Youngdon Choi; Junghwan Choi
- Web page: https://patentgrep.com/patent/US11443785B2

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1066: {Output synchronization}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1093: {Input synchronization}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- H03K 19/01742: {by means of a pull-up or down element}
- H03K 19/1774: {for global signals, e.g. clock, reset}
- H03K 19/1776: for memories
- G11C 2207/101: Analog or multilevel bus
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A memory device includes a memory cell array and a data input and output circuit configured to output a data signal (DQ signal) including data read from the memory cell array and a data strobe signal (DQS signal) including a toggle pattern associated with an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn), wherein n is an integer greater than or equal to 4.

## Claims

### Claim 1

A memory device comprising:
a memory cell array; and
a data input and output circuit configured to output a data signal (DQ signal) comprising data read from the memory cell array, and a data strobe signal (DQS signal) comprising a toggle pattern corresponding to an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn),
wherein n is an integer greater than or equal to 4.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the operating condition of the memory device comprises at least one of an operating frequency of the memory device, a power state of the memory device, or a pattern of the DQ signal.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the data input and output circuit is further configured to output first and second DQS signals comprising first and second toggle patterns in response to first and second read commands received under different operating conditions of the memory device, respectively.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein a toggle pattern interval of the first toggle pattern is different from a toggle pattern interval of the second toggle pattern.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein at least one of a first toggle low level and a first toggle high level of the first toggle pattern is different from a second toggle low level and a second toggle high level of the second toggle pattern.

### Claim 6 (depends on 1)

The memory device of claim 1,
wherein the DQ signal comprises first and second data patterns associated with respective data unit groups,
wherein the first and second data patterns are different from each other, and
wherein the DQS signal comprises first and second toggle patterns corresponding to the first and second data patterns, respectively, and different from each other.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first and second toggle patterns comprise at least three voltage levels.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the memory device is configured to receive, from a memory controller, a signal indicating the operating condition of the memory device.

### Claim 9 (depends on 1)

The memory device of claim 1,
wherein the data input and output circuit comprises a DQS generator configured to generate the DQS signal, and
wherein the DQS generator comprises:
a PAM circuit configured to generate a level selection signal associated with the DQS signal, based on the operating condition of the memory device;
a level selector configured to generate a plurality of pull-up bit signals and a plurality of pull-down bit signals based on the level selection signal; and
a driver configured to output the DQS signal based on the plurality of pull-up bit signals and the plurality of pull-down bit signals.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the data input and output circuit further comprises a slope adjustment circuit connected to the driver and configured to adjust a level transition slope of the DQS signal based on a toggle level interval of the toggle pattern.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the slope adjustment circuit comprises:
a pulse generator configured to generate first and second pulse signals associated with a transition timing comprising rising and/or fall edges of the toggle pattern, based on the level selection signal; and
an auxiliary circuit configured to generate an adjustment signal for adjusting the level transition slope, based on the first and second pulse signals, and further configured to provide the adjustment signal to the driver.

### Claim 12 (depends on 9)

The memory device of claim 9,
wherein the driver comprises two pull-up circuits and two pull-down circuits when the PAMn comprises PAM 4, and
wherein the two pull-up circuits comprise a plurality of pMOS transistors and the two pull-down circuits comprise a plurality of nMOS transistors.

### Claim 13 (depends on 9)

The memory device of claim 9, wherein the data input and output circuit further comprises a transmitter configured to output the DQ signal synchronized with the DQS signal.

### Claim 14

A memory system comprising:
a memory device comprising a memory cell array; and
a memory controller configured to control a memory operation of the memory device,
wherein the memory device and the memory controller each transmit and receive a data strobe signal (DQS signal) comprising a different toggle pattern according to an operating condition of the memory system based on n-level pulse amplitude modulation (PAMn), and
wherein n is an integer greater than or equal to 4.

### Claim 15 (depends on 14)

The memory system of claim 14,
wherein the toggle pattern has a toggle level interval adjusted according to PAMn based on the operating condition of the memory system, and
wherein the operating condition of the memory device comprises at least one of an operating frequency of the memory device, a power state of the memory device, or a pattern of the DQS signal.

### Claim 16 (depends on 14)

The memory system of claim 14, wherein the toggle pattern has a toggle low level and a toggle high level adjusted according to PAMn based on the operating condition of the memory system.

### Claim 17 (depends on 14)

The memory system of claim 14,
wherein the memory device and the memory controller are configured to transmit and receive, to and from each other, a data signal (DQ signal) comprising data for programming to the memory cell array or data read from the memory cell array,
wherein the DQ signal comprises a plurality of data patterns that are associated with respective data unit groups, and
wherein the DQS signal comprises a plurality of toggle patterns corresponding to the plurality of data patterns, respectively, and comprising at least three voltage levels.

### Claim 18

A method of operating a memory device, the method comprising:
receiving a first read command corresponding to a first operating condition;
outputting, in response to the first read command, a first data signal (DQ signal) and a first data strobe signal (DQS signal) based on n-level pulse amplitude modulation (PAMn) and corresponding to the first operating condition;
receiving a second read command corresponding to a second operating condition that is different from the first operating condition; and
outputting, in response to the second read command, a second DQ signal and a second DQS signal based on PAMn and corresponding to the second operating condition,
wherein the first DQS signal has a first toggle pattern different from a second toggle pattern of the second DQS signal.

### Claim 19 (depends on 18)

The method of claim 18, wherein a toggle level interval of the first DQS signal is different from a toggle level interval of the second DQS signal.

### Claim 20 (depends on 18)

The method of claim 18, wherein at least one of a first toggle low level and a first toggle high level of the first DQS signal is different from a second toggle low level and a second toggle high level of the second DQS signal.