# US 11,443,783 B2 · Semiconductor device

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- Number: US 11,443,783 B2
- Document ID: US11443783B2
- Status: Granted
- Kind: B2
- Application number: 17/308,300
- Filed: 2021-05-05
- Published: 2022-01-20
- Granted: 2022-09-13
- Earliest claimed: 2020-07-16
- Assignees: Fujitsu Limited
- Applicants: Fujitsu Limited
- Inventors: Kohei Michibata
- Web page: https://patentgrep.com/patent/US11443783B2

## CPC

- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/1087: {Data input latches}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device includes a memory device configured to have a first buffer and a second buffer, the first buffer storing a plurality of requests sent to a plurality of destinations, the second buffer storing identification information of the entry associated with a first destination of a first request written to first buffer; and an entry selector configured to identify the first destination from the plurality of destinations when the identification information of the entry is stored in the second buffer, and to read the first request from the plurality of requests stored in the first buffer by using the first destination.

## Claims

### Claim 1

A semiconductor device comprising:
a memory device configured to have a first buffer and a second buffer, the first buffer including a plurality of entries respectively storing a plurality of requests sent to a plurality of destinations, the second buffer being associated with a first destination of a first request written to first buffer, the second buffer storing identification information on at least one of the plurality of entries; and
an entry selector configured to identify the first destination from the plurality of destinations in response to the identification information of the at least one of the plurality of entries being stored in the second buffer, and to read the first request from the plurality of requests stored in the first buffer by using the first destination.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the entry selector is configured to:
store the identification information on the plurality of entries of the first buffer in which the plurality of requests have been written, in a plurality of second buffers that correspond to the plurality of destinations of the plurality of requests, in response to writing of the plurality of requests into the first buffer,
determine whether or not transmission of the plurality of requests to the plurality of destinations is feasible,
perform arbitration for some of the plurality of destinations determined to be available for the transmission of the plurality of requests,
specify one destination to which one of the plurality of requests is to be sent, from among the some of the plurality of destinations, and
read the one of the plurality of requests from one of the plurality of entries of the first buffer specified by the identification information on the one of the plurality of entries acquired from one of the second buffers that corresponds to the one destination.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second buffer is controlled by first-in, first-out (FIFO).

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the memory device is configured to have position information that indicates a position of an oldest piece of the identification information on one of the plurality of entries in each of a plurality of second buffers; and have position information that indicates a position of a free area into which a next one of the plurality of requests is supposed to be written in each of the second buffers.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the entry selector is configured to determine that transmission of the plurality of requests to the plurality of destinations is feasible when data storage areas at the plurality of destinations have free areas.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the entry selector is configured to manage usage state for each of the plurality of entries of the first buffer.