# US 11,443,780 B2 · Vertical access line multiplexor

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- Number: US 11,443,780 B2
- Document ID: US11443780B2
- Status: Granted
- Kind: B2
- Application number: 17/172,257
- Filed: 2021-02-10
- Published: 2022-08-11
- Granted: 2022-09-13
- Earliest claimed: 2021-02-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yuan He; Beau D. Barry; Tae H. Kim; Christopher J. Kawamura
- Web page: https://patentgrep.com/patent/US11443780B2

## CPC

- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 13/0028: {Word-line or row circuits}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 16/30: Power supply circuits
- G11C 16/32: Timing circuits
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4094: Bit-line management or control circuits
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C 2213/71: Three dimensional array
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

## Claims

### Claim 1

An apparatus, comprising:
an access line multiplexor formed under a plurality of vertically stacked tiers of memory cells, the multiplexor comprising:
a first terminal of a first n-type metal oxide semiconductor (nMOS) transistor coupled to a vertical access line and to a first terminal of a second nMOS transistor;
a second terminal of the first nMOS transistor coupled to a horizontal access line; and
a second terminal of the second nMOS transistor coupled to a negative power supply;
wherein the vertical access line is coupled to a plurality of gates of a plurality of memory cells in the vertically stacked tiers;
wherein the horizontal access line is coupled to a plurality of additional vertical access lines via a plurality of additional multiplexors; and
wherein the apparatus further comprises control circuitry configured to simultaneously:
cause the multiplexor to electrically couple the vertical access line to the horizontal access line; and
cause the plurality of additional multiplexors to electrically decouple the plurality of additional vertical access lines from the horizontal access line.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the control circuitry is further configured to simultaneously activate a horizontal sense line coupled to a particular memory cell in a particular tier, wherein the particular memory cell is also coupled to the vertical access line.

### Claim 3

A memory device, comprising:
an array of memory cells comprising:
a plurality of vertically stacked tiers of memory cells;
a plurality of vertical access lines coupled to the plurality of tiers; and
a respective plurality horizontal sense lines coupled to each of the plurality of tiers;
semiconductor under the array circuitry, comprising a plurality of multiplexers, wherein each multiplexor comprises:
a first terminal of a first transistor coupled to a respective vertical access line and to a first terminal of a second transistor;
a second terminal of the first transistor coupled to a horizontal access line; and
a second terminal of the second transistor coupled to a negative power supply; and
a plurality of sense amplifiers each coupled to a respective subset of the plurality of horizontal sense lines;
wherein the respective subset of the plurality of horizontal sense lines comprises one sense line in each of the plurality of tiers; and
wherein the respective subset of the plurality of horizontal sense lines is coupled to the respective sense amplifier via a staircase connection.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein each multiplexor is configured such that deactivation of the first transistor and activation of the second transistor causes the respective vertical access line to be electrically coupled to the negative power supply.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein each multiplexor is configured such that activation of first transistor and deactivation of the second transistor causes the respective vertical access line to be electrically coupled to the horizontal access line.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein the first transistor comprises an n-type metal oxide semiconductor (nMOS) transistor; and
wherein the second transistor comprises an nMOS transistor.

### Claim 7 (depends on 3)

The memory device of claim 3, wherein a gate of the first transistor is coupled to a control circuit configured to apply to the gate at a particular time any one of:
a negative supply voltage;
a positive supply voltage; and
a positive supply voltage plus a threshold voltage of the first transistor.

### Claim 8 (depends on 3)

The memory device of claim 3, wherein a gate of the second transistor is coupled to a control circuit configured to apply to the gate at a particular time any one of:
a negative supply voltage; and
a voltage that is greater than the negative supply voltage.

### Claim 9 (depends on 3)

The memory device of claim 3, further comprising a positive power supply coupled to the horizontal access line;
wherein the horizontal access line is under the array and coupled to a subset of the plurality of vertical access lines.

### Claim 10 (depends on 3)

The memory device of claim 3, wherein the horizontal access line is one of a plurality of horizontal access lines under the array.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein each of the plurality of horizontal access lines is coupled to respective access line driver; and
wherein the respective access line driver is located outside of the array and horizontally adjacent to the array.

### Claim 12

A method of sensing a memory cell in an array, comprising:
among a plurality of vertical access lines physically coupled to each of a plurality of vertically stacked tiers of memory cells and to a horizontal access line:
electrically coupling a particular vertical access line of the plurality of vertical access lines to the horizontal access line via a particular multiplexer in semiconductor under the array circuitry, wherein the particular vertical access line is coupled to the memory cell;
electrically decoupling a remainder of the plurality of vertical access lines from the horizontal access line via respective other multiplexors in the semiconductor under the array circuitry;
activating a horizontal sense line coupled to the memory cell; and
sensing the memory cell with a sense amplifier coupled to the horizontal sense line via a staircase connection, wherein the sense amplifier is horizontally adjacent to the plurality of vertically stacked tiers of memory cells.

### Claim 13 (depends on 12)

The method of claim 12, wherein electrically coupling the particular vertical access line to the horizontal access line comprises:
applying a first signal to a gate of a first n-type metal oxide semiconductor (nMOS) transistor of the particular multiplexor for a first period of time;
applying a second signal to the gate of the first nMOS transistor for a second period of time;
applying the first signal to the gate of the first nMOS transistor for a third period of time; and
applying a third signal to a gate of a second nMOS transistor of the particular multiplexor during the first, second, and third periods of time.

### Claim 14 (depends on 13)

The method of claim 13, wherein applying the first signal to the gate of the first nMOS transistor for the first period of time comprises applying the first signal for an amount of time sufficient to cause time dependent dielectric breakdown of a gate oxide of the first nMOS transistor.

### Claim 15 (depends on 13)

The method of claim 13, wherein applying the first signal comprises applying a positive supply voltage plus a threshold voltage of the first nMOS transistor; and
wherein applying the second signal comprises applying the positive supply voltage.

### Claim 16 (depends on 15)

The method of claim 15, wherein applying the third signal comprises applying a negative supply voltage.

### Claim 17 (depends on 13)

The method of claim 13, wherein electrically decoupling the remainder of the plurality of vertical access lines from the horizontal access line comprises:
applying the third signal to a respective gate of a respective first nMOS transistor of each of the respective other multiplexors for the first, second, and third periods of time; and
applying a fourth signal to a respective gate of a respective second nMOS transistor of each of the respective other multiplexors for the first, second, and third periods of time.