# US 11,443,779 B2 · Drive strength calibration for multi-level signaling

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- Number: US 11,443,779 B2
- Document ID: US11443779B2
- Status: Granted
- Kind: B2
- Application number: 17/241,876
- Filed: 2021-04-27
- Published: 2021-10-14
- Granted: 2022-09-13
- Earliest claimed: 2018-08-21
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Peter Mayer; Wolfgang Anton Spirkl; Michael Dieter Richter; Martin Brox; Thomas Hein
- Web page: https://patentgrep.com/patent/US11443779B2

## CPC

- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 11/5657: {using ferroelectric storage elements}
- G11C 29/021: {in voltage or current generators}
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/12005: {comprising voltage or current generators}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/4401: {for self repair}
- G11C 11/565: {using capacitive charge storage elements}
- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

## Claims

### Claim 1

A method, comprising:
generating, by a driver of a memory controller using an initial drive strength, a first voltage on a data channel electrically between the memory controller and a memory device;
receiving, from the memory device, a feedback signal indicating a difference between the first voltage on the data channel and a reference voltage corresponding to a symbol level of a pulse amplitude modulation scheme; and
generating, by the driver using an adjusted drive strength based at least in part on the feedback signal, a second voltage on the data channel.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
configuring the driver to use the adjusted drive strength based at least in part on the feedback signal.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
determining, based at least in part on the feedback signal, that the first voltage is less than the reference voltage, wherein configuring the driver comprises:
configuring, based at least in part on the determination, the driver with a second impedance to generate the second voltage, wherein the second impedance is less than a first impedance used to generate the first voltage.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
determining, based at least in part on the feedback signal, that the first voltage is greater than the reference voltage, and wherein configuring the driver comprises:
configuring, based at least in part on the determination, the driver with a second impedance to generate the second voltage, wherein the second impedance is greater than a first impedance used to generate the first voltage, and wherein and the adjusted drive strength is based at least in part on the second impedance.

### Claim 5 (depends on 1)

The method of claim 1, wherein the feedback signal comprises a first logic value, the method further comprising:
receiving a second feedback signal that indicates a second difference between the second voltage and the reference voltage, wherein the second feedback signal comprises a second logic value; and
determining that the reference voltage is between the first voltage and the second logic value based at least in part on the second logic value being different than the first logic value.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
setting the drive strength for the symbol level based at least in part on the determining that the reference voltage is between the first voltage and the second voltage.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
receiving a second feedback signal indicating a second difference between the second voltage and the reference voltage; and
generating, by the driver using a further-adjusted drive strength based at least in part on the second feedback signal, a third voltage on the data channel.

### Claim 8 (depends on 7)

The method of claim 7, wherein the feedback signal comprises a first logic value and the second feedback signal comprises a second logic value, the method further comprising:
determining that the second logic value is the same as the first logic value, wherein the third voltage is generated based at least in part on the determination.

### Claim 9 (depends on 1)

The method of claim 1, wherein the difference comprises a mathematical difference between the first voltage and the reference voltage or a relationship between the first voltage and the reference voltage.

### Claim 10

A method, comprising:
determining, using a sense component of a memory device, a first difference between a reference voltage and a first voltage on a data channel electrically between the memory device and a memory controller, the reference voltage corresponding to a symbol level of a pulse amplitude modulation scheme;
transmitting to the memory controller a first feedback signal indicating the first difference between the first voltage and the reference voltage, and
determining a second difference between the reference voltage and a second voltage on the data channel based at least in part on transmitting the first feedback signal to the memory controller.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
transmitting, to the memory device based at least in part on determining the second difference, a second feedback signal indicating the second difference.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
receiving, based at least in part on transmitting the second feedback signal, an indication that calibration for the symbol level is complete; and
determining, based at least in part on receiving the indication that the calibration for the symbol level is complete, a third difference between a third voltage on the data channel and a second reference voltage corresponding to a second symbol level.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
determining a first logic value based at least in part on the first difference, wherein the first feedback signal comprises the first logic value; and
determining a second logic value based at least in part on the second difference, wherein the second feedback signal comprises the second logic value.

### Claim 14 (depends on 13)

The method of claim 13, wherein determining the first difference comprises:
determining that the first voltage is less than the reference voltage, and wherein determining the second difference comprises:
determining that the second voltage is less than the reference voltage, wherein the first logic value and the second logic value are the same logic value.

### Claim 15 (depends on 13)

The method of claim 13, wherein determining the first difference comprises:
determining that the first voltage is less than the reference voltage, and wherein determining the second difference comprises:
determining that the second voltage is greater than the reference voltage, wherein the first logic value and the second logic value are different logic values.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
comparing the first voltage with the reference voltage, wherein the first difference is determined based at least in part on comparing the first voltage with the reference voltage; and
comparing the second voltage with the reference voltage, wherein the second difference is determined based at least in part on comparing the second voltage with the reference voltage.

### Claim 17

An apparatus, comprising:
a memory controller comprising a driver, the memory controller operable to cause the apparatus to:
generate, by the driver using an initial drive strength, a first voltage on a data channel electrically between the memory controller and a memory device;
receive, from the memory device, a feedback signal indicating a difference between the first voltage on the data channel and a reference voltage corresponding to a symbol level of a pulse amplitude modulation scheme; and
generate, by the driver using an adjusted drive strength based at least in part on the feedback signal, a second voltage on the data channel.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the memory controller is operable to cause the apparatus to:
determine, based at least in part on the feedback signal, that the first voltage is less than the reference voltage; and
configure, based at least in part on the determination, the driver with a second impedance to generate the second voltage, wherein the second impedance is less than a first impedance used to generate the first voltage.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein the memory controller is operable to cause the apparatus to:
determine, based at least in part on the feedback signal, that the first voltage is greater than the reference voltage; and
configure, based at least in part on the determination, the driver with a second impedance to generate the second voltage, wherein the second impedance is greater than a first impedance used to generate the first voltage, and wherein and the adjusted drive strength is based at least in part on the second impedance.

### Claim 20 (depends on 17)

The apparatus of claim 17, wherein feedback signal comprises a first logic value, and wherein the memory controller is operable to cause the apparatus to:
receive a second feedback signal that indicates a second difference between the second voltage and the reference voltage, wherein the second feedback signal comprises a second logic value; and
determine that the reference voltage is between the first voltage and the second logic value based at least in part on the second logic value being different than the first logic value.