# US 11,443,776 B2 · Memory system design for signal integrity crosstalk reduction with asymmetry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,776 B2 - Document ID: US11443776B2 - Status: Granted - Kind: B2 - Application number: 16/442,208 - Filed: 2019-06-14 - Published: 2020-12-17 - Granted: 2022-09-13 - Earliest claimed: 2019-06-14 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Sunil Gupta - Web page: https://patentgrep.com/patent/US11443776B2 ## CPC - G06F 30/394: Routing (G06F30/396 takes precedence) - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - H05K 1/0228: {Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245)} - H05K 1/0243: {Printed circuits associated with mounted high frequency components} - H10W 90/00: Package configurations - H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines} - H05K 2201/09227: Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting - H05K 2201/09236: Parallel layout - H05K 2201/10159: Memory - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces. ## Claims ### Claim 1 An integrated circuit, comprising: a printed circuit board (PCB); a package substrate interconnected on the PCB, the package substrate comprising parallel signal traces arranged in an asymmetric routing; a system on chip (SoC) die interconnected on the package substrate, the SOC die comprising a parallel memory interface coupled to the parallel signal traces of the package substrate through package interconnects; and a memory device package on the SoC die and coupled to the parallel memory interface of the SoC die through the parallel signal traces arranged in the asymmetric routing of the package substrate, in which a variable spacing is provided between the parallel signal traces for a majority portion of the parallel signal traces of a longest leg of an internal signal integrity channel. ### Claim 2 (depends on 1) The integrated circuit of claim 1, in which a trace space between an inner one of the parallel signal traces is greater than the trace space between an outer one of the parallel signal traces. ### Claim 3 (depends on 2) The integrated circuit of claim 2, in which a first uneven trace space between the inner one of parallel signal traces and a closest trace is greater than a second uneven trace space between any two other of the parallel signal traces. ### Claim 4 (depends on 1) The integrated circuit of claim 1, in which a smallest uneven trace space equals a distance between a furthest parallel signal trace from a center of the parallel memory interface and the next furthest parallel signal trace. ### Claim 5 (depends on 1) The integrated circuit of claim 1, in which the parallel memory interface comprises a plurality of channels, and each channel comprises a first data byte channel and a second data byte channel, the first data byte channel and the second data byte channel comprising uneven trace spaces b1, b2, b3, and b4, in which b1>b2>b3>b4. ### Claim 6 (depends on 1) The integrated circuit of claim 1, in which the parallel memory interface comprises a low power double data rate (LPDDR) memory interface. ### Claim 7 (depends on 1) The integrated circuit of claim 1, in which the memory device package comprises a volatile memory device and/or a non-volatile memory (NVM) device. ### Claim 8 (depends on 1) The integrated circuit of claim 1, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communications systems (PCS) unit, a portable data unit, a fixed location data unit, and/or an automotive electronic system. ### Claim 9 An integrated circuit, comprising: a package substrate comprising parallel signal traces arranged in an asymmetric routing; a die interconnected on the package substrate and having a parallel memory interface coupled to the plurality of parallel signal traces of the package substrate through package interconnects, in which the parallel signal traces of the package substrate are spaced apart based on uneven trace spaces, in which a trace space between inner ones of the parallel signal traces is greater than a trace space between outer ones of the parallel signal traces for a majority portion of the parallel signal traces of a longest leg of an internal signal integrity channel; and a memory device package stacked on the die and coupled to the parallel memory interface of the die through the asymmetric routing of the package substrate. ### Claim 10 (depends on 9) The integrated circuit of claim 9, in which a first uneven trace space between the inner ones of the plurality of parallel signal traces and a closest signal trace is greater than a second uneven trace space between any two other of the plurality of parallel signal traces. ### Claim 11 (depends on 9) The integrated circuit of claim 9, in which a smallest uneven trace space b4 equals a distance between a furthest one of the plurality of parallel signal trace from a center of the parallel memory interface and a next furthest one of the plurality of parallel signal traces. ### Claim 12 (depends on 9) The integrated circuit of claim 9, in which the parallel memory interface comprises a plurality of channels, and each channel comprises a first data byte channel and a second data byte channel, the first data byte channel and the second data byte channel comprising uneven trace spaces b1, b2, b3, and b4, in which b1>b2>b3>b4.