# US 11,443,697 B2 · Driving circuit and display device including the same

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- Number: US 11,443,697 B2
- Document ID: US11443697B2
- Status: Granted
- Kind: B2
- Application number: 17/191,607
- Filed: 2021-03-03
- Published: 2021-06-24
- Granted: 2022-09-13
- Earliest claimed: 2014-02-14
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Ki-Myeong Eom
- Web page: https://patentgrep.com/patent/US11443697B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- H01Q 9/0407: {Substantially flat resonant element parallel to ground plane, e.g. patch antenna (dipole H01Q9/285; monopole H01Q9/40)}
- H01Q 19/00: Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic {(combination of horns with slotted waveguide array H01Q13/0233)}
- H01Q 19/13: the primary radiating source being a single radiating element, e.g. a dipole, a slot, a waveguide termination (H01Q19/15 takes precedence)
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1315: {comprising structures specially adapted for lowering the resistance}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/023: using energy recovery or conservation
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

## Claims

### Claim 1

A scan driver comprising:
a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits comprising:
a first transistor configured to receive an input signal in synchronization with a first clock signal and to respond to an enable level of the input signal to output a second clock signal as a corresponding scan signal;
a first wire configured to transfer a first voltage;
a second wire configured to transfer a second voltage;
a second transistor electrically connected between the first transistor and the first wire; and
a third transistor electrically connected between a gate of the second transistor and the second wire;
wherein a width of the first wire is greater than a width of the second wire, and
wherein the first voltage and the second voltage are DC voltages, and the first voltage is higher than the second voltage.

### Claim 2 (depends on 1)

The scan driver of claim 1, further comprising:
a third wire for transferring the first clock signal.

### Claim 3 (depends on 2)

The scan driver of claim 2, wherein a gate of the third transistor is electrically connected to the third wire.

### Claim 4 (depends on 1)

The scan driver of claim 1, further comprising:
a fourth transistor electrically connected between a gate of the first transistor and the first wire.

### Claim 5 (depends on 4)

The scan driver of claim 4, wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor.

### Claim 6 (depends on 4)

The scan driver of claim 4, further comprising:
a fifth transistor electrically connected between the fourth transistor and the gate of the first transistor.

### Claim 7 (depends on 6)

The scan driver of claim 6, further comprising:
a fourth wire for transferring the second clock signal.

### Claim 8 (depends on 7)

The scan driver of claim 7, wherein a gate of the fifth transistor is electrically connected to the fourth wire.

### Claim 9 (depends on 1)

The scan driver of claim 1, further comprising:
a sixth transistor electrically connected between a gate of the second transistor and a gate of the third transistor.

### Claim 10 (depends on 9)

The scan driver of claim 9, wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor.

### Claim 11 (depends on 1)

The scan driver of claim 1, further comprising:
a seventh transistor to transfer the input signal to a gate of the first transistor in synchronization with the first clock signal.

### Claim 12 (depends on 1)

The scan driver of claim 1, further comprising:
a first capacitor connected between a gate of the first transistor and a source electrode of the first transistor.

### Claim 13 (depends on 1)

The scan driver of claim 1, further comprising:
a second capacitor connected between the gate of the second transistor and a source electrode of the second transistor.

### Claim 14

A display device comprising:
a scan driver configured to generate a plurality of scan signals; and
a plurality of pixels to receive a plurality of data voltages according to the plurality of scan signals,
wherein the scan driver comprises:
a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits comprising:
a first transistor configured to receive an input signal in synchronization with a first clock signal and to respond to an enable level of the input signal to output a second clock signal as a corresponding scan signal;
a first wire configured to transfer a first voltage;
a second wire configured to transfer a second voltage;
a second transistor electrically connected between the first transistor and the first wire;
a third transistor electrically connected between a gate of the second transistor and the second wire;
wherein a width of the first wire is greater than a width of the second wire, and
wherein the first voltage and the second voltage are DC voltages, and the first voltage is higher than the second voltage.

### Claim 15 (depends on 14)

The display device of claim 14, further comprising:
a fourth transistor electrically connected between a gate of the first transistor and the first wire.

### Claim 16 (depends on 15)

The display device of claim 15, further comprising:
a fifth transistor electrically connected between the fourth transistor and the gate of the first transistor.

### Claim 17 (depends on 14)

The display device of claim 14, further comprising:
a sixth transistor electrically connected between a gate of the second transistor and a gate of the third transistor.

### Claim 18 (depends on 14)

The display device of claim 14, further comprising:
a seventh transistor to transfer the input signal to a gate of the first transistor in synchronization with the first clock signal.

### Claim 19 (depends on 14)

The display device of claim 14, further comprising:
a first capacitor connected between the gate of the first transistor and a source electrode of the first transistor.

### Claim 20 (depends on 14)

The display device of claim 14, further comprising:
a second capacitor connected between the gate of the second transistor and a source electrode of the second transistor.