# US 11,443,681 B2 · Gate driver and display apparatus including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,681 B2 - Document ID: US11443681B2 - Status: Granted - Kind: B2 - Application number: 15/412,691 - Filed: 2017-01-23 - Published: 2017-08-31 - Granted: 2022-09-13 - Earliest claimed: 2016-02-29 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Cholho Kim; Gunwoo Yang; Hyunyoung Choi; Jihoon Yang; Yongwoo Lee - Web page: https://patentgrep.com/patent/US11443681B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 3/296: Driving circuits for producing the waveforms applied to the driving electrodes - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal. ## Claims ### Claim 1 A gate driver comprising: a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, wherein the first clock signal repeatedly alternates between the low level and the high level; and a pull-down boosting circuit configured to output a first off voltage to a clock terminal receiving the first clock signal in the second duration in response to a second clock signal repeatedly alternating between the low level and the high level, wherein the pull-up-pull-down circuit comprises a first transistor including a control electrode connected to a first node, an input electrode connected to the clock terminal and an output electrode connected to a gate terminal outputting the gate signal, and wherein the pull-down boosting circuit comprises an eighteenth transistor including a control electrode connected to a second clock terminal receiving the second clock signal repeatedly alternating between the low level and the high level, an input electrode directly connected to a first off terminal receiving the first off voltage and an output electrode constantly and directly connected to the clock terminal, wherein a level of the first off voltage is substantially the same as the low level of the first clock signal. ### Claim 2 (depends on 1) The gate driver of claim 1, wherein the first off voltage is a direct current DC voltage. ### Claim 3 (depends on 1) The gate driver of claim 1, wherein the second clock signal is the first clock signal inverted. ### Claim 4 (depends on 1) The gate driver of claim 1, further comprising: a pull-up-pull-down control circuit configured to control an operation of the pull-up-pull-down circuit in response to a previous carry signal and a next carry signal, wherein the pull-up-pull-down circuit, the pull-down boosting circuit, and the pull-up-pull-down control circuit form a current stage, wherein the previous carry signal is output by a previous stage that is located before the current stage, wherein the next carry signal is output by a next stage that is located after the current stage, and wherein the previous stage and the next stage include the same elements as the current stage. ### Claim 5 (depends on 4) The gate driver of claim 4, wherein the pull-up-pull-down circuit comprises a first transistor, wherein a first control electrode of the first transistor is connected to the pull-up-pull-down control circuit, wherein a first input electrode of the first transistor is configured to receive the first clock signal, and wherein a first output electrode of the first transistor is configured to output the gate signal. ### Claim 6 (depends on 5) The gate driver of claim 5, wherein the pull-down boosting circuit comprises a second transistor, wherein a second control electrode of the second transistor is configured to receive the second clock signal, wherein a second input electrode of the second transistor is configured to receive the first off voltage, and a second output electrode of the second transistor is connected to the first input electrode. ### Claim 7 (depends on 4) The gate driver of claim 4, wherein the first off voltage is commonly applied to every stage. ### Claim 8 (depends on 1) The gate driver of claim 1, wherein the input electrode is directly connected to the first off terminal. ### Claim 9 (depends on 1) The gate driver of claim 1, further comprising a fourth transistor including a control electrode and an input electrode commonly connected to a previous carry signal. ### Claim 10 (depends on 9) The gate driver of claim 9, further comprising a ninth transistor including a control electrode connected to a next carry signal, an input electrode connected to a second off terminal receiving a second off voltage, and an output electrode connected to an output node of the fourth transistor. ### Claim 11 A gate driver comprising: a pull-up circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration; a pull-down circuit configured to pull down the gate signal to a first off voltage in a second duration in response to a next carry signal output by a next stage; an inverting circuit configured to generate a current inverting signal based on the first clock signal and a second off voltage; and a pull-down boosting circuit configured to output the second off voltage to a clock terminal receiving the first clock signal that repeatedly alternates between a low level and the high level in the second duration in response to a previous inverting signal output by a previous stage, wherein the pull-up circuit comprises a first transistor including a control electrode connected to a first node, an input electrode connected to the clock terminal, and an output electrode connected to a gate output terminal outputting the gate signal, and wherein the pull-down boosting circuit comprises an eighteenth transistor including a control electrode connected to a previous inverting node receiving the previous inverting signal, an input electrode directly connected to a second off terminal receiving the second off voltage and an output electrode constantly and directly connected to the clock terminal, wherein a level of the first off voltage is substantially the same as the low level of the first clock signal. ### Claim 12 (depends on 11) The gate driver of claim 11, wherein the second off voltage is a direct current DC voltage. ### Claim 13 (depends on 11) The gate driver of claim 11, wherein the inverting signal of the previous stage has a low level during the first duration and has a high level during the second duration. ### Claim 14 A display apparatus comprising: a data driver configured to generate a data voltage based on input image data; a gate driver comprising: a first transistor connected between a first clock terminal and a gate output terminal and comprising a first control electrode connected to a first node, a first input electrode connected to the first clock terminal and a first output electrode connected to the gate output terminal; a fourth transistor connected between a previous carry terminal and the first node and comprising a fourth control electrode connected to the previous carry terminal; a ninth transistor connected between the first node and a first off terminal and comprising a ninth control electrode connected to a next carry terminal; a tenth transistor connected between the first node and the first off terminal and comprising a tenth control electrode connected to the first node; and an eighteenth transistor connected between the first clock terminal and the first off terminal and comprising an eighteenth control electrode connected to an inversion terminal, an eighteenth input electrode directly connected to the first off terminal and an eighteenth output electrode constantly and directly connected to the first clock terminal; and a display panel configured to display an image based on the data voltage and the gate signal, wherein a first clock signal that repeatedly alternates between a low level and a high level is configured to be applied to the first clock terminal, a gate signal is configured to be output to the gate output terminal, a first off voltage is configured to be applied to the first off terminal, a previous carry signal is configured to be applied to the previous carry terminal, a next carry signal is configured to be applied to the next carry terminal, and an inversion signal is configured to be applied to the inversion terminal, wherein the inversion signal has a low level during the first clock signal has a high level, wherein the eighteenth input electrode of the eighteenth transistor is connected to a ninth input electrode of the ninth transistor, wherein a level of the first off voltage is substantially the same as the low level of the first clock signal. ### Claim 15 (depends on 14) The display apparatus of claim 14, wherein the first off voltage is a direct current DC voltage. ### Claim 16 (depends on 14) The display apparatus of claim 14, wherein the inversion signal is the first clock signal inverted. ### Claim 17 (depends on 14) The display apparatus of claim 14, wherein the gate driver further comprises: a seventh transistor connected between the first clock terminal and the first node and comprising a seventh control electrode connected to a second node; an eighth transistor connected between the first node and the first off terminal and comprising an eighth control electrode connected to a current carry terminal; a twelfth transistor connected between the first clock terminal and the second node and comprising a twelfth control electrode connected to the first clock terminal; a thirteenth transistor connected between the second node and the first off terminal and comprising a thirteenth control electrode connected to the current carry terminal; a first capacitor connected between the first clock terminal and the second node; and a second capacitor connected between the first node and the second node, wherein a current carry signal is configured to be output to the current carry terminal. ### Claim 18 (depends on 14) The display apparatus of claim 14, wherein the gate driver further comprises: a second transistor connected between the gate output terminal and a second off terminal comprising a second control electrode connected to the next carry terminal. ### Claim 19 (depends on 14) The display apparatus of claim 14, wherein the first off voltage is commonly applied to every stage.