# US 11,443,675 B2 · Shift register circuit and pixel driving device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,675 B2 - Document ID: US11443675B2 - Status: Granted - Kind: B2 - Application number: 17/468,720 - Filed: 2021-09-08 - Published: 2022-07-14 - Granted: 2022-09-13 - Earliest claimed: 2021-01-12 - Assignees: Au Optronics Corporation - Applicants: AU Optronics Corporation - Inventors: Che-Chia Chang; Yi-Jung Chen; Shang-Jie Wu; Yu-Chieh Kuo; Hsien-Chun Wang; Ming-Hung Chuang; Mei-Yi Li; Sin-An Lin; Chen-Ying Chou - Web page: https://patentgrep.com/patent/US11443675B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/064: by time modulation of the brightness of the illumination source - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A shift register circuit includes a driving signal generating circuit, a coupling circuit, and a sweep signal generating circuit. The driving signal generating circuit is configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal. The coupling circuit is coupled to the driving signal generating circuit. The coupling circuit is configured to transmit the low voltage source. The sweep signal generating circuit is coupled to the coupling circuit. The sweep signal generating circuit is configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal. A waveform of the sweep signal includes an oblique waveform. The first high voltage source and the second high voltage source are electrically independent of each other. ## Claims ### Claim 1 A shift register circuit, comprising: a driving signal generating circuit, configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal according to the plurality of first clock signals, the low voltage source, the initial signal, and the first high voltage source; a coupling circuit, coupled to the driving signal generating circuit, and configured to transmit the low voltage source; and a sweep signal generating circuit, coupled to the coupling circuit, and configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal according to the second clock signal, the low voltage source, and the second high voltage source, wherein a waveform of the sweep signal comprises an oblique waveform, wherein the first high voltage source and the second high voltage source are electrically independent of each other. ### Claim 2 (depends on 1) The shift register circuit of claim 1, wherein the coupling circuit comprises a capacitor, wherein the capacitor comprises a first end and a second end, wherein the first end of the capacitor is coupled to a first node, wherein the second end of the capacitor is coupled to the sweep signal generating circuit, wherein the capacitor is configured to stabilize the sweep signal. ### Claim 3 (depends on 2) The shift register circuit of claim 2, wherein the coupling circuit comprises a first transistor, wherein the first transistor comprises a first end, a second end, and a control end, wherein the first end of the first transistor is configured to receive the low voltage source, wherein the first transistor is turned on in response to the control end receiving the initial signal, wherein the second end of the first transistor is configured to transmit the low voltage source to the first node. ### Claim 4 (depends on 3) The shift register circuit of claim 3, wherein the driving signal generating circuit comprises a second transistor, wherein the second transistor comprises a first end, a second end, and a control end, wherein the first end of the second transistor is configured to receive the low voltage source, wherein the second transistor is turned on in response to the control end receiving to the initial signal, wherein the second end of the second transistor is configured to output the driving signal, wherein the first end of the first transistor is coupled to the second end of the second transistor. ### Claim 5 (depends on 1) The shift register circuit of claim 1, wherein waveforms of the first clock signals are different from waveforms of the second clock signal, wherein the second clock signal comprises a first signal and a second signal, wherein the first signal comprises a horizontal waveform, wherein the second signal comprises an oblique waveform. ### Claim 6 (depends on 5) The shift register circuit of claim 5, wherein a period of the sweep signal is about six times units of scan time of pixels of a display, wherein a period of the first signal ranges from 0.5 unit of scan time to one unit of scan time. ### Claim 7 A pixel driving device, comprising: at least one data line, wherein the at least one data line comprises a first side and a second side, wherein the first side is opposite to the second side; and at least one shift register circuit, comprising: a driving signal generating circuit, configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal according to the plurality of first clock signals, the low voltage source, the initial signal, and the first high voltage source; a coupling circuit, coupled to the driving signal generating circuit, and configured to transmit the low voltage source; and a sweep signal generating circuit, coupled to the coupling circuit, and configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal according to the second clock signal, the low voltage source, and the second high voltage source, wherein a waveform of the sweep signal comprises an oblique waveform, wherein the first high voltage source and the second high voltage source are electrically independent of each other; wherein the driving signal generating circuit is located at the first side of the at least one data line, wherein the sweep signal generating circuit is located at the second side of the at least one data line. ### Claim 8 (depends on 7) The pixel driving device of claim 7, wherein the coupling circuit comprises a capacitor, wherein the capacitor comprises a first end and a second end, wherein the first end of the capacitor is coupled to a first node, wherein the second end of the capacitor is coupled to the sweep signal generating circuit, wherein the capacitor is configured to stabilize the sweep signal. ### Claim 9 (depends on 8) The pixel driving device of claim 8, wherein the coupling circuit comprises a first transistor, wherein the first transistor comprises a first end, a second end, and a control end, wherein the first end of the first transistor is configured to receive the low voltage source, wherein the first transistor is turned on in response to the control end receiving the initial signal, wherein the second end of the first transistor is configured to transmit the low voltage source to the first node. ### Claim 10 (depends on 9) The pixel driving device of claim 9, wherein the driving signal generating circuit comprises a second transistor, wherein the second transistor comprises a first end, a second end, and a control end, wherein the first end of the second transistor is configured to receive the low voltage source, wherein the second transistor is turned on in response to the control end receiving the initial signal, wherein the second end of the second transistor is configured to output the driving signal, wherein the first end of the first transistor is coupled to the second end of the second transistor.