# US 11,443,673 B2 · Electro-optical device and electronic apparatus

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- Number: US 11,443,673 B2
- Document ID: US11443673B2
- Status: Granted
- Kind: B2
- Application number: 17/362,493
- Filed: 2021-06-29
- Published: 2021-12-30
- Granted: 2022-09-13
- Earliest claimed: 2020-06-30
- Assignees: Seiko Epson Corporation
- Applicants: Seiko Epson Corporation
- Inventors: Nariya Takahashi
- Web page: https://patentgrep.com/patent/US11443673B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3685: {Details of drivers for data electrodes}
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An electro-optical device includes an electro-optical panel including first to n-th (n is an integer of 2 or greater) data line blocks with each data line block including a first data line group and a second data line group, a first circuit device, and a second circuit device. The first circuit device drives, in an i-th phase of phase development drive, the first data line group of an i-th data line block of the first to n-th data line blocks, and the second circuit device drives, in the i-th phase of the phase development drive, the second data line group of the i-th data line block of the first to n-th data line blocks.

## Claims

### Claim 1

An electro-optical device comprising:
an electro-optical panel including first to n-th data line blocks, each of the data line blocks including a first data line group and a second data line group, n being an integer of 2 or greater;
a first circuit device configured to drive the electro-optical panel; and
a second circuit device configured to drive the electro-optical panel, wherein
the first to n-th data line blocks are, along a scanning line direction of the electro-optical panel, arranged side-by-side so that an i+1-th data line block is located next to an i-th data line block, i being an integer satisfying 1≤i<n,
the first circuit device is configured to, in an i-th phase of phase development drive, drive the first data line group of the i-th data line block of the first to n-th data line blocks,
the second circuit device is configured to, in the i-th phase of the phase development drive, drive the second data line group of the i-th data line block of the first to n-th data line blocks, and
there is a difference between a timing at which the first circuit device outputs an image signal and a timing at which the second circuit device outputs an image signal.

### Claim 2 (depends on 1)

The electro-optical device according to claim 1, wherein
a data line of the first data line group and the data line of the second data line group of each of the data line blocks are arranged alternately in the scanning line direction.

### Claim 3 (depends on 1)

The electro-optical device according to claim 1, wherein
when each of the data line blocks includes m data lines, the first data line group is a collection of m/2 of the data lines arranged consecutively along the scanning line direction, and the second data line group is a collection of m/2 of the data lines arranged consecutively along the scanning line direction, m being an integer of 2 or greater.

### Claim 4 (depends on 1)

The electro-optical device according to claim 1, wherein
the electro-optical panel includes first to n-th switch circuits, and
an i-th switch circuit of the first to n-th switch circuits is configured to, in the i-th phase of the phase development drive, select the i-th data line block, output a first data signal group of the first circuit device to the first data line group of the i-th data line block, and output a second data signal group of the second circuit device to the second data line group of the i-th data line block.

### Claim 5 (depends on 4)

The electro-optical device according to claim 4, comprising a timing adjustment circuit, wherein
the first circuit device includes a first control signal generation circuit configured to generate and output a first control signal group,
the second circuit device includes a second control signal generation circuit configured to generate and output a second control signal group,
the first control signal group includes a first enable signal configured to determine an on period of the first to n-th switch circuits,
the second control signal group includes a second enable signal configured to determine the on period of the first to n-th switch circuits, and
the timing adjustment circuit is configured to perform timing adjustment of the first enable signal and the second enable signal.

### Claim 6 (depends on 5)

The electro-optical device according to claim 5, wherein
the electro-optical panel includes a control circuit configured to control on/off of the first to n-th switch circuits, and
in the i-th phase of the phase development drive, the control circuit is configured to, when the first enable signal is active, cause the i-th switch circuit to select the first data line group of the i-th data line block, and when the second enable signal is active, cause the i-th switch circuit to select the second data line group of the i-th data line block.

### Claim 7 (depends on 5)

The electro-optical device according to claim 5, wherein
the timing adjustment circuit is configured to generate a first delay signal by delaying the first enable signal, generate a second delay signal by delaying the second enable signal, and output, to the electro-optical panel, any one of the first enable signal or the first delay signal, and any one of the second enable signal or the second delay signal.

### Claim 8 (depends on 1)

The electro-optical device according to claim 1, comprising a timing adjustment circuit, wherein
the first circuit device includes a first control signal generation circuit configured to generate and output a first control signal group,
the second circuit device includes a second control signal generation circuit configured to generate and output a second control signal group, and
the timing adjustment circuit is configured to perform timing adjustment of the first control signal group and the second control signal group, and output, to the electro-optical panel, the first control signal group and the second control signal group after the timing adjustment.

### Claim 9 (depends on 5)

The electro-optical device according to claim 5, comprising a flexible substrate configured to couple the first circuit device and the second circuit device to the electro-optical panel, wherein
the timing adjustment circuit is provided at the flexible substrate.

### Claim 10

An electronic apparatus comprising:
a processor;
a memory; and
an electro-optical device comprising:
an electro-optical panel including first to n-th data line blocks, each of the data line blocks including a first data line group and a second data line group, n being an integer of 2 or greater;
a first circuit device configured to drive the electro-optical panel; and
a second circuit device configured to drive the electro-optical panel, wherein
the first to n-th data line blocks are, along a scanning line direction of the electro-optical panel, arranged side-by-side so that an i+1-th data line block is located next to an i-th data line block, i being an integer satisfying 1≤i<n,
the first circuit device is configured to, in an i-th phase of phase development drive, drive the first data line group of the i-th data line block of the first to n-th data line blocks,
the second circuit device is configured to, in the i-th phase of the phase development drive, drive the second data line group of the i-th data line block of the first to n-th data line blocks, and
there is a difference between a timing at which the first circuit device outputs an image signal and a timing at which the second circuit device outputs an image signal.