# US 11,443,668 B2 · Driving circuit comprising redundant clock signal line and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,668 B2 - Document ID: US11443668B2 - Status: Granted - Kind: B2 - Application number: 16/767,136 - Filed: 2020-04-23 - Published: 2022-04-21 - Granted: 2022-09-13 - Earliest claimed: 2020-03-22 - Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Zhida Xu; Ilgon Kim; Bin Zhao; Xin Zhang; Jun Zhao - Web page: https://patentgrep.com/patent/US11443668B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 2300/0413: Details of dummy pixels or dummy lines in flat panels - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0209: Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display - G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A driving circuit and a display panel are provided. In a driving circuit structure, a clock signal line group includes a plurality of clock signal lines, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines. A non-high frequency signal line is provided on two sides of the clock signal line group. A redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line, and a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line. ## Claims ### Claim 1 A driving circuit, comprising: a signal generator; a driving circuit unit; a clock signal line group comprising a plurality of clock signal lines, wherein an input end of the clock signal line is electrically connected to the signal generator, and an output end of the clock signal line is electrically connected to the driving circuit unit, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines; a non-high frequency signal line, wherein an input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is provided on two sides of the clock signal line group; and a redundant clock signal line, wherein an input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line; a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line; wherein the redundant clock signal line has a second pitch with an adjacent clock signal line, the second pitch is equal to the first pitch, a width of the redundant clock signal line is less than a width of the clock signal line, the non-high frequency signal line has a third pitch with an adjacent redundant clock signal line, and the third pitch is greater than the second pitch. ### Claim 2 (depends on 1) The driving circuit according to claim 1, wherein a thickness of the redundant clock signal line and a thickness of the clock signal line are equal. ### Claim 3 (depends on 1) The driving circuit according to claim 1, wherein material of the redundant clock signal line is the same as material of the clock signal line. ### Claim 4 (depends on 1) The driving circuit according to claim 1, wherein the non-high frequency signal line is a low-frequency signal line or a DC signal line. ### Claim 5 (depends on 4) The driving circuit according to claim 4, wherein an output end of the low-frequency signal line is electrically connected to the driving circuit unit or a common electrode. ### Claim 6 A display panel, comprising: a driving circuit disposed in a non-display area of the display panel, wherein the driving circuit comprising: a signal generator; a driving circuit unit; a clock signal line group comprising a plurality of clock signal lines, wherein an input end of the clock signal line is electrically connected to the signal generator, and an output end of the clock signal line is electrically connected to the driving circuit unit, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines; a non-high frequency signal line, wherein an input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is provided on two sides of the clock signal line group; and a redundant clock signal line, wherein an input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line; a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line; wherein the redundant clock signal line has a second pitch with an adjacent clock signal line, the second pitch is equal to the first pitch, a width of the redundant clock signal line is less than a width of the clock signal line, the non-high frequency signal line has a third pitch with an adjacent redundant clock signal line, and the third pitch is greater than the second pitch. ### Claim 7 (depends on 6) The display panel according to claim 6, wherein a thickness of the redundant clock signal line and a thickness of the clock signal line are equal. ### Claim 8 (depends on 6) The display panel according to claim 6, wherein material of the redundant clock signal line is the same as material of the clock signal line. ### Claim 9 (depends on 6) The display panel according to claim 6, wherein the non-high frequency signal line is a low-frequency signal line or a DC signal line. ### Claim 10 (depends on 9) The display panel according to claim 9, wherein an output end of the low-frequency signal line is electrically connected to the driving circuit unit or a common electrode.