# US 11,443,479 B1 · Snapshot arbitration techniques for memory requests > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,479 B1 - Document ID: US11443479B1 - Status: Granted - Kind: B1 - Application number: 17/324,857 - Filed: 2021-05-19 - Granted: 2022-09-13 - Earliest claimed: 2021-05-19 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Winnie W. Yeung; Leela Kishore Kothamasu; Zelin Zhang; Guanlan Xu; Eddie M. Robinson - Web page: https://patentgrep.com/patent/US11443479B1 ## CPC - G06T 15/83: Phong shading - G06F 13/1668: {Details of memory controller} - G06F 13/3625: {using a time dependent access} - G06T 1/60: Memory management - G06T 15/005: {General purpose rendering architectures} - G06T 15/04: Texture mapping - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption. ## Claims ### Claim 1 An apparatus, comprising: queue circuitry that implements multiple queues configured to queue requests to access a memory bus; control circuitry configured to: in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time; generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time; and arbitrate between requests from the multiple queues to select requests to access the memory bus, wherein the arbitration is based on snapshots to which requests from the multiple queues belong. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the control circuitry is configured to select all available requests from the first snapshot before selecting any requests from the second snapshot that are not in the first snapshot. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the control circuitry implements a credit system; and wherein the control circuitry is configured to select one or more requests from the second snapshot, that are not in the first snapshot, while one or more requests from the first snapshot are still queued based on one or more requests from the first snapshot being unavailable due to lack of credits. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the control circuitry is configured to provide a greater priority weight to requests from the first snapshot than requests from the second snapshot that are not in the first snapshot. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the control circuitry is configured to select all requests from the first snapshot before selecting any requests from the second snapshot that are not in the first snapshot. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the control circuitry is configured to use weighted round-robin arbitration among the queues prior to detecting the first threshold condition and round-robin arbitration among queues for requests in the first snapshot subsequent to detecting the first threshold condition. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the control circuitry includes at least three sets of counters configured to maintain information that indicates current numbers of requests in three or more snapshots for respective ones of the queues, wherein the control circuitry is configured to update the counters based on queued requests winning arbitration. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein one or more of the queues maintain ordering among requests of one or more virtual channels that are shared by multiple client circuits. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising: a cache that includes a first portion associated with a first processor sub-unit and a second portion associated with a second processor sub-unit; and router circuitry configured to route cache access requests from the second processor sub-unit to the first portion of the cache; wherein the queue circuitry and control circuitry are included in the router circuitry. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the cache includes at least three portions associated with respective processor sub-units and the router circuitry is configured to route cache access requests in at least three directions. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the queue circuitry and control circuitry are included in circuitry that routes memory access requests for one or more shader cores of a graphics processor. ### Claim 12 A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes: queue circuitry that implements multiple queues configured to queue requests to access a memory bus; control circuitry configured to: in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time; generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time; and arbitrate between requests from the multiple queues to select requests to access the memory bus, wherein the arbitration is based on snapshots to which requests from the multiple queues belong. ### Claim 13 (depends on 12) The non-transitory computer readable storage medium of claim 12, wherein the control circuitry is configured to provide higher priority to requests in the first snapshot than to requests in the second snapshot. ### Claim 14 (depends on 12) The non-transitory computer readable storage medium of claim 12, wherein the control circuitry is configured to select all available requests from the first snapshot before selecting any requests from the second snapshot that are not in the first snapshot. ### Claim 15 (depends on 12) The non-transitory computer readable storage medium of claim 12, wherein the control circuitry is configured to use weighted round-robin arbitration among the queues prior to detecting the first threshold condition and round-robin arbitration among queues for requests in the first snapshot subsequent to detecting the first threshold condition. ### Claim 16 (depends on 12) The non-transitory computer readable storage medium of claim 12, wherein the control circuitry includes at least three sets of counters configured to maintain information that indicates current numbers of requests in three or more snapshots for respective ones of the queues, wherein the control circuitry is configured to update the counters based on queued requests winning arbitration. ### Claim 17 (depends on 12) The non-transitory computer readable storage medium of claim 12, wherein one or more of the queues maintain ordering among requests of one or more virtual channels that are shared by multiple client circuits. ### Claim 18 A method, comprising: generating, by control circuitry, a first snapshot that indicates numbers of requests in respective queues of multiple queues at a first time, wherein the generating is performed in response to detecting a first threshold condition associated with queue circuitry that includes the multiple queues; generating, by the control circuitry, a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time; and arbitrating, by the control circuitry, between requests from the multiple queues to select requests to access a memory bus, wherein the arbitrating is based on snapshots to which requests from the multiple queues belong. ### Claim 19 (depends on 18) The method of claim 18, wherein arbitrating includes selecting all available requests from the first snapshot before selecting any requests from the second snapshot that are not in the first snapshot. ### Claim 20 (depends on 18) The method of claim 18, wherein the control circuitry uses weighted round-robin arbitration among the queues prior to detecting the first threshold condition and uses round-robin arbitration among queues for requests in the first snapshot subsequent to detecting the first threshold condition.