# US 11,443,405 B2 · Mechanism to accelerate graphics workloads in a multi-core computing architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,405 B2 - Document ID: US11443405B2 - Status: Granted - Kind: B2 - Application number: 17/322,146 - Filed: 2021-05-17 - Published: 2021-11-04 - Granted: 2022-09-13 - Earliest claimed: 2016-08-05 - Assignees: Intel IP Corporation - Applicants: Intel IP Corporation - Inventors: Carsten Benthin; Sven Woop; Ingo Wald - Web page: https://patentgrep.com/patent/US11443405B2 ## CPC - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/505: {considering the load} - G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 ) - G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)} - G06F 13/1657: {Access to multiple memories} - G06T 1/60: Memory management - G06T 2200/28: involving image processing hardware - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core. ## Claims ### Claim 1 An apparatus comprising: a processor including a plurality of processor cores, the processor including: a first processor core to process a first plurality of threads; a second processor core to process a second plurality of threads; and a first cache memory coupled to the first processor core and the second processor core; a first field programmable gate array (FPGA) coupled to the first processor core, the first FPGA to accelerate execution of workloads processed at the first processor core; a second FPGA coupled to the second processor core, the second FPGA to accelerate execution of workloads processed at the second processor core; and a second cache memory coupled with and shared between the first processor core, second processor core, and the first FPGA, wherein the first FPGA is an independent agent to the second cache memory. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first processor core is to select a first workload to be accelerated at the first FPGA and the second processor core is to select a second workload to be accelerated at the second FPGA. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein logic gates of the first FPGA are programmed to execute a first type of workload, logic gates of the second FPGA are programmed to execute a second type of workload, and the logic gates of the first FPGA and the second FPGA are reprogrammable during the lifetimes of their respective workloads. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first processor core includes a first controller to control execution of the first FPGA, and the second processor core includes a second controller to control execution of the second FPGA. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the first controller and the second controller are to control execution of the first FPGA and the second FPGA via memory-mapped I/O (MMIO) regions. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the first controller and the second controller are to control execution of the first FPGA and the second FPGA via dedicated processor instructions. ### Claim 7 (depends on 6) The apparatus of claim 6, further comprising: a third processor core coupled to the first FPGA and the second cache memory. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the first FPGA is to accelerate execution of workloads processed at the first processor core and the third processor core. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the first processor core is a central processing unit and the second processor core is a graphics processing unit. ### Claim 10 (depends on 9) The apparatus of claim 9, further comprising: a first memory device coupled to the first processor core, the third processor core, and the first FPGA via the second cache memory; and a second memory device coupled to the second processor core and the second FPGA. ### Claim 11 (depends on 10) The apparatus of claim 10, further comprising: a fourth processor core coupled to the second FPGA and the second memory device, wherein the second FPGA accelerates execution of workloads processed at the second processor core and the fourth processor core. ### Claim 12 A method comprising: processing a first plurality of threads via a first processor core of a processor including a plurality of processor cores; processing a second plurality of threads via a second processor core of the processor; while processing the first plurality of threads and the second plurality of threads, reading data from a cache memory coupled with the first processor core and the second processor core; accelerating a first workload processed by the first plurality of threads via a first field programmable gate array (FPGA) coupled to the first processor core, wherein the first FPGA is to accelerate execution of workloads processed at the first processor core and is an independent agent to a second cache memory shared between the first processor core, second processor core, and first FPGA; and accelerating a second workload processed by the second plurality of threads via a second FPGA coupled to the second processor core, wherein the second FPGA is to accelerate execution of workloads processed at the second processor core. ### Claim 13 (depends on 12) The method of claim 12, further comprising selecting, by the first processor core, the first workload to be accelerated at the first FPGA and selecting, by the second processor core, the second workload to be accelerated at the second FPGA. ### Claim 14 (depends on 12) The method of claim 12, further comprising: programming logic gates of the first FPGA to execute a first type of workload, the first type of workload associated with the first workload; and programming logic gates of the second FPGA to execute a second type of workload, the second type of workload associated with the second workload. ### Claim 15 (depends on 14) The method of claim 14, further comprising reprogramming the logic gates of the first FPGA during the lifetime of the first workload or reprogramming the logic gates of the second FPGA during the lifetime of the second workload. ### Claim 16 (depends on 12) The method as in claim 12, wherein the first processor core is a central processing unit and the second processor core is a graphics processing unit. ### Claim 17 A data processing system comprising: a peripheral bus interconnect; and a processor coupled with the peripheral bus interconnect, the processor including: a first processor core to process a first plurality of threads; a second processor core to process a second plurality of threads; and a cache memory coupled to the first processor core and the second processor core; a first field programmable gate array (FPGA) coupled to the first processor core, the first FPGA to accelerate execution of workloads processed at the first processor core, wherein the first processor core is to select a first workload to be accelerated at the first FPGA; a second FPGA coupled to the second processor core, the second FPGA to accelerate execution of workloads processed at the second processor core, wherein the second processor core is to select a second workload to be accelerated at the second FPGA; and a second cache memory coupled with and shared between the first processor core, second processor core, and the first FPGA, wherein the first FPGA is an independent agent to the second cache memory. ### Claim 18 (depends on 17) The data processing system of claim 17, wherein logic gates of the first FPGA are programmed to execute a first type of workload, logic gates of the second FPGA are programmed to execute a second type of workload, and the logic gates of the first FPGA and the second FPGA are reprogrammable during the lifetimes of their respective workloads. ### Claim 19 (depends on 18) The data processing system of claim 18, wherein the first processor core includes a first controller to control execution of the first FPGA, the second processor core includes a second controller to control execution of the second FPGA, the first controller and the second controller are to control execution of the first FPGA and the second FPGA via memory-mapped I/O (MMIO) regions and dedicated processor instructions. ### Claim 20 (depends on 19) The data processing system of claim 19, further comprising: a third processor core coupled to the first FPGA; and wherein the second cache memory is accessible by the third processor core, the first FPGA is to accelerate execution of workloads processed at the first processor core and the third processor core, the first processor core is a central processing unit, and the second processor core is a graphics processing unit.