# US 11,443,175 B2 · Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network

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- Number: US 11,443,175 B2
- Document ID: US11443175B2
- Status: Granted
- Kind: B2
- Application number: 16/150,606
- Filed: 2018-10-03
- Published: 2020-01-16
- Granted: 2022-09-13
- Earliest claimed: 2018-07-11
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran; Vipin Tiwari; Nhan Do
- Web page: https://patentgrep.com/patent/US11443175B2

## CPC

- G06N 3/065: Analogue means
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06F 3/061: {Improving I/O performance}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06N 3/044: Recurrent networks, e.g. Hopfield networks
- G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/048: Activation functions
- G06N 3/08: Learning methods
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 16/0425: {comprising cells containing a merged floating gate and select transistor}
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G06N 3/045: Combinations of networks
- G11C 2211/563: Multilevel memory reading aspects
- G11C 2213/15: Current-voltage curve
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. The embodiments are able to compensate for slope differences during both sub-threshold and linear operation of reference transistors.

## Claims

### Claim 1

A method of adjusting a reference transistor in a flash memory system, comprising:
receiving an input voltage;
multiplying the input voltage by a coefficient to generate an output voltage;
applying the output voltage to a gate of the reference transistor; and
using the reference transistor in a sense operation to determine a value stored in a selected memory cell.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
coupling the input voltage to gates of memory cells in a memory array.

### Claim 3 (depends on 1)

The method of claim 1, wherein the reference transistor operates in a sub-threshold region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the reference transistor operates in a linear region.

### Claim 5 (depends on 2)

The method of claim 2, wherein the reference transistor operates in a sub-threshold region.

### Claim 6 (depends on 2)

The method of claim 2, wherein the reference transistor operates in linear region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the input voltage is connected to a drain of the reference transistor.

### Claim 8 (depends on 7)

The method of claim 7, wherein an input current is connected to a drain of the reference transistor to produce the input voltage.

### Claim 9 (depends on 1)

The method of claim 1, wherein a slope of a current-voltage characteristic curve of the reference transistor and a slope of a current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

### Claim 10 (depends on 1)

The method of claim 1, wherein the input voltage is coupled to a normalizing circuit.

### Claim 11 (depends on 10)

The method of claim 10, wherein an output of the normalizing circuit is connected to the selected memory cell.

### Claim 12 (depends on 10)

The method of claim 10, wherein the normalizing circuit is a current mirror circuit.

### Claim 13 (depends on 10)

The method of claim 10, wherein the value from the memory cells are bitline current or sourceline current.

### Claim 14 (depends on 1)

The method of claim 1, wherein the memory cells are non-volatile.

### Claim 15 (depends on 1)

The method of claim 1, wherein the multiplying is performed by a driver circuit coupled to the gate of the reference transistor.

### Claim 16 (depends on 1)

The method of claim 1, wherein the multiplying is performed by a pair of input capacitors coupled to the gate of the reference transistor.

### Claim 17 (depends on 1)

The method of claim 1, wherein the multiplying is performed by a pair of operational amplifiers coupled to the gate of the reference transistor.

### Claim 18

A method of adjusting a characteristic curve of a reference memory cell in a flash memory system, comprising:
receiving an input voltage;
multiplying the input voltage by a coefficient to generate an output voltage;
applying the output voltage to a gate of the reference memory cell; and
using the reference memory cell in a sense operation to determine a value stored in a selected memory cell.

### Claim 19 (depends on 18)

The method of claim 18, wherein a slope of a current-voltage characteristic curve of the reference memory cell and a slope of a current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

### Claim 20 (depends on 19)

The method of claim 19, wherein the reference memory cell operates in a sub-threshold region.

### Claim 21 (depends on 19)

The method of claim 19, wherein the reference memory cell operates in a linear region.

### Claim 22 (depends on 18)

The method of claim 18, wherein the reference memory cell operates in sub-threshold regions.

### Claim 23 (depends on 18)

The method of claim 18, wherein the reference memory cell operates in a linear region.

### Claim 24 (depends on 18)

The method of claim 18, wherein the input voltage is connected to a drain of the reference memory cell.

### Claim 25 (depends on 18)

The method of claim 18, wherein the reference memory cell is non-volatile.

### Claim 26 (depends on 18)

The method of claim 18, wherein the multiplying is performed by a driver circuit coupled to the gate of the reference memory cell.

### Claim 27 (depends on 18)

The method of claim 18, wherein the multiplying is performed by a pair of input capacitors coupled to the gate of the reference memory cell.

### Claim 28 (depends on 18)

The method of claim 18, wherein the multiplying is performed by a pair of operational amplifiers coupled to the gate of the reference memory cell.