# US 11,443,174 B2 · Machine learning accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,174 B2 - Document ID: US11443174B2 - Status: Granted - Kind: B2 - Application number: 16/682,466 - Filed: 2019-11-13 - Published: 2020-05-14 - Granted: 2022-09-13 - Earliest claimed: 2018-11-13 - Assignees: Imec Vzw; Katholieke Universiteit Leuven, KU LEUVEN R&D - Applicants: Imec Vzw; Katholieke Universiteit Leuven, KU LEUVEN R&D - Inventors: Daniele Garbin; Simone Lavizzari - Web page: https://patentgrep.com/patent/US11443174B2 ## CPC - G06N 3/063: using electronic means - G06N 3/065: Analogue means - G11C 13/0026: {Bit-line or column circuits} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2213/71: Three dimensional array - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals. ## Claims ### Claim 1 A neural network circuit for providing a threshold weighted sum of input signals, the neural network circuit comprising: at least two arrays of transistors with programmable threshold voltage, each transistor of the at least two arrays storing a synaptic weight as the programmable threshold voltage and having a control electrode for receiving an activation input signal, each transistor of the at least two arrays providing an output current for either a positive weighted current component in an array of a set of first arrays or a negative weighted current component in an array of a set of second arrays; an associated reference network for each array of transistors configured to provide a reference signal to be combined with the positive weight current component or the negative weight current component of the transistors of the associated array, the reference signal having opposite sign compared to the positive weight current component or negative weight current component of the associated array; and at least one bitline for receiving the combined positive current component or negative current component, each combined with their associated reference signals. ### Claim 2 (depends on 1) The neural network circuit according to claim 1, wherein the transistors of the at least two arrays connect to a single bitline for receiving the positive current weighted component and the negative weighted current component combined with reference signals. ### Claim 3 (depends on 1) The neural network circuit according to claim 1, wherein a comparator compares the combined positive current component and negative current component combined with reference signals to a pre-determined reference value. ### Claim 4 (depends on 1) The neural network circuit according to claim 1, wherein first transistors of one of a first array connect to a first bitline, different from a second bitline, to which second transistors of a second arrays connect, the first bitline and second bitline, respectively, configured to receive a combined positive current component and associated reference signal, or the combined negative weighted current component and associated reference signal. ### Claim 5 (depends on 4) The neural network circuit according to claim 4, further comprising a differential amplifier configured to amplify a difference between the combined positive weighted current component and negative reference signal with the combined negative weighted current component and positive reference signal. ### Claim 6 (depends on 1) The neural network circuit according to claim 1, wherein the transistors of one of the arrays are laid out in a single physical plane of an electronic component. ### Claim 7 (depends on 6) The neural network circuit according to claim 6, wherein a plurality of planes of transistors are stacked vertically. ### Claim 8 (depends on 1) The neural network circuit according to claim 1, wherein the positive weighted current component and negative weighted current component are provided by driving multiple transistors in parallel. ### Claim 9 (depends on 1) The neural network circuit according to claim 1, wherein the transistors generating the positive weighted current component or negative weighted current component are laid out on a horizontal plane of a three-dimensional array. ### Claim 10 (depends on 1) The neural network circuit according to claim 1, wherein the transistors are operated in subthreshold region and act as current sources controlled by an input gate voltage. ### Claim 11 (depends on 1) The neural network circuit according to claim 1, wherein the reference network is implemented as one or more transistors in parallel. ### Claim 12 (depends on 1) The neural network circuit according to any of claim 1, wherein the reference network is implemented as one or more programmable resistive memories in parallel.