# US 11,443,172 B2 · Synapse array of neuromorphic device including synapses having ferro-electric field effect transistors and operation method of the same

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- Number: US 11,443,172 B2
- Document ID: US11443172B2
- Status: Granted
- Kind: B2
- Application number: 15/810,160
- Filed: 2017-11-13
- Published: 2018-12-06
- Granted: 2022-09-13
- Earliest claimed: 2017-06-05
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hyung-Dong Lee
- Web page: https://patentgrep.com/patent/US11443172B2

## CPC

- G06N 3/063: using electronic means
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A synapse array of a neuromorphic device is provided. The synapse array may include a pre-synaptic neuron; a row line extending from the pre-synaptic neuron in a row direction; a post synaptic neuron; a column line extending from the post-synaptic neuron in a column direction; and a synapse disposed at an intersection region between the row line and the column line. The synapse may include an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body; and a resistive element having a first node electrically connected to the source electrode of the n-FeFET and electrically connected to the source electrode of the p-FeFET, and the n-FeFET and the p-FeFET are electrically connected in series.

## Claims

### Claim 1

A synapse array of a neuromorphic device comprising:
a pre-synaptic neuron;
a row line extending from the pre-synaptic neuron in a row direction;
a post synaptic neuron;
a column line extending from the post-synaptic neuron in a column direction; and
a synapse disposed at an intersection region between the row line and the column line,
wherein the synapse comprises
an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
an input port electrically connected in common with the row line, the gate electrode of the n-FeFET, and the gate electrode of the p-FeFET; and
a resistive element having two nodes, a first node electrically connected in common to the source electrodes of the n-FeFET and the p-FeFET and a second node electrically connected to the column line, and
wherein
the resistive element is a fixed resistor having a fixed resistance,
the drain electrode of the n-FeFET is electrically connected to a power supply node to provide a fixed power supply voltage, and
the drain electrode of the p-FeFET is electrically connected to a ground voltage node to provide a fixed ground voltage.

### Claim 2 (depends on 1)

The synapse array of claim 1,
wherein the body of the n-FeFET is electrically connected to the source electrode of the n-FeFET, and
wherein the body of the p-FeFET is electrically connected to the source electrode of the p-FeFET.

### Claim 3

A synapse array of a neuromorphic device comprising:
a plurality of pre-synaptic neurons;
a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction;
a plurality of post-synaptic neurons;
a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction; and
a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
wherein each of the plurality of synapses comprises:
an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
an input port electrically connected in common to the gate electrode of the n-FeFET and the gate electrode of the p-FeFET; and
a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
wherein
each of the plurality of row lines comprises a first synaptic row line and a second synaptic row line extending from a pre-synaptic neuron in parallel with each other,
each of the first synaptic row lines is electrically connected to the drain electrode of the n-FeFET to provide a fixed power supply voltage to the drain electrode of the n-FeFET,
each of the second synaptic row lines is electrically connected to the drain electrode of the p-FeFET to provide a fixed ground voltage to the drain electrode of the p-FeFET, and
the resistive element is a fixed resistor having a fixed resistance.

### Claim 4 (depends on 3)

The synapse array of claim 3,
wherein the body of and the source electrode of the n-FeFET and the body of and the source electrode of the p-FeFET are electrically connected to each other.

### Claim 5

A synapse array of a neuromorphic device comprising:
a plurality of pre-synaptic neurons;
a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction, and each row line including a first synaptic row line, a second synaptic row line, and a third synaptic row line extending in parallel with each other;
a plurality of post-synaptic neurons;
a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction; and
a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
wherein each of the plurality of synapses comprises:
an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
an input port electrically connected in common to the third synaptic row line, the gate electrode of the n-FeFET and the gate electrode of the p-FeFET; and
a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
wherein
each of the first synaptic row lines provides a fixed power supply voltage to the drain electrode of the n-FeFET,
each of the second synaptic row lines provides a fixed ground voltage to the drain electrode of the p-FeFET
each of the third synaptic row lines is electrically connected to the gate electrode of each of the n-FeFET and the p-FeFET, and
the resistive element is a fixed resistor having a fixed resistance.

### Claim 6 (depends on 5)

The synapse array of claim 5,
wherein the body of and the source electrode of the n-FeFET and the body of and the source electrode of the p-FeFET are electrically connected to each other.

### Claim 7

A method of operating a neuromorphic device comprising: setting a first polarization voltage and a second polarization voltage of the neuromorphic device, wherein the first polarization voltage is greater than the second polarization voltage, and
applying a read voltage to the neuromorphic device to enable current flow, wherein the neuromorphic device comprises:
a pre-synaptic neuron;
a row line extending from the pre-synaptic neuron in a row direction;
a post synaptic neuron;
a column line extending from the post-synaptic neuron in a column direction; and
a synapse disposed at an intersection region between the row line and the column line,
wherein the synapse comprises
an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
an input port electrically connected in common with the row line, the gate electrode of the n-FeFET, and the gate electrode of the p-FeFET; and
a resistive element having two nodes, a first node electrically connected in common to the source electrodes of the n-FeFET and the p-FeFET and a second node electrically connected to the column line, and
wherein the resistive element is a fixed resistor having a fixed resistance,
the drain electrode of the n-FeFET is electrically connected to a power supply node to provide a fixed power supply voltage,
the drain electrode of the p-FeFET is electrically connected to a ground voltage node to provide a fixed ground voltage,
the first polarization voltage polarizes the gate electrode of the n-FeFET,
the second polarization voltage polarizes the gate electrode of the p-FeFET, and
the read voltage is applied to the input port.

### Claim 8 (depends on 7)

The method of claim 7,
wherein the body of and the source electrode of the n-FeFET and the body of and the source electrode of the p-FeFET are electrically connected to each other.

### Claim 9

A method of operating a neuromorphic device comprising:
setting a first polarization voltage and a second polarization voltage of the neuromorphic device,
wherein the first polarization voltage is greater than the second polarization voltage, and applying a read voltage to the neuromorphic device to enable current flow,
wherein the neuromorphic device comprises:
a plurality of pre-synaptic neurons;
a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction;
a plurality of post-synaptic neurons;
a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction; and
a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
wherein each of the plurality of synapses comprises:
an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
an input port electrically connected in common to the gate electrode of the n-FeFET and the gate electrode of the p-FeFET; and
a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
wherein
each of the plurality of row lines includes a first synaptic row line, a second synaptic row line, and a third synaptic row line extending from the plurality of pre-synaptic neurons in parallel with each other,
each of the first synaptic row lines provides a fixed power supply voltage to the drain electrode of the n-FeFET,
each of the second synaptic row lines provides a fixed ground voltage to the drain electrode of the p-FeFET,
each of the third synaptic row lines is electrically connected to the gate electrode of each of the n-FeFET and the gate electrode of each of the p-FeFET,
the resistive element is a fixed resistor having a fixed resistance,
the first polarization voltage polarizes the gate electrode of the n-FeFET,
the second polarization voltage polarizes the gate electrode of the p-FeFET, and
the read voltage is applied to the input port.

### Claim 10 (depends on 9)

The method of claim 9,
wherein the body of and the source electrode of the n-FeFET and the body of and the source electrode of the p-FeFET are electrically connected to each other.

### Claim 11

A method of operating a neuromorphic device comprising:
setting a first polarization voltage and a second polarization voltage of the neuromorphic device, wherein the second polarization voltage is greater than the first polarization voltage, and
applying a read voltage to the neuromorphic device to enable current flow,
wherein the neuromorphic device comprises:
a plurality of pre-synaptic neurons;
a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction;
a plurality of post-synaptic neurons;
a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction; and
a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
wherein each of the plurality of synapses comprises:
an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
an input port electrically connected in common to the gate electrode of the n-FeFET and the gate electrode of the p-FeFET; and
a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
wherein
each of the plurality of row lines includes a first synaptic row line, a second synaptic row line, and a third synaptic row line extending from the plurality of pre-synaptic neurons in parallel with each other,
each of the first synaptic row lines provides a fixed power supply voltage to the drain electrode of the n-FeFET,
each of the second synaptic row lines provides a fixed ground voltage to the drain electrode of the p-FeFET,
each of the third synaptic row lines is electrically connected to the gate electrode of each the n-FeFET and the gate electrode of each the p-FeFET,
the resistive element is a fixed resistor having a fixed resistance,
the first polarization voltage polarizes the gate electrode of the n-FeFET,
the second polarization voltage polarizes the gate electrode of the p-FeFET, and
the read voltage is applied to the input port.

### Claim 12 (depends on 11)

The method of claim 11,
wherein the body of and the source electrode of the n-FeFET and the body of and the source electrode of the p-FeFET are electrically connected to each other.