# US 11,443,091 B1 · Data processing engines with cascade connected cores > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,091 B1 - Document ID: US11443091B1 - Status: Granted - Kind: B1 - Application number: 16/945,006 - Filed: 2020-07-31 - Granted: 2022-09-13 - Earliest claimed: 2020-07-31 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Peter McColgan; Baris Ozgul; David Clarke; Tim Tuan; Juan J. Noguera Serra; Goran H. K. Bilski; Jan Langer; Sneha Bhalchandra Date; Stephan Munz; Jose Marques - Web page: https://patentgrep.com/patent/US11443091B1 ## CPC - G06F 15/7867: {with reconfigurable architecture} - G06F 30/343: Logical level - G06F 9/30098: {Register arrangements} - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs. ## Claims ### Claim 1 An integrated circuit, comprising: a plurality of data processing engines (DPEs) each including a core configured to perform computations; wherein a first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core, wherein the input cascade connection is coupled to a plurality of source cores of the plurality of DPEs; wherein the input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is coupled to a cascade output of a different one of the plurality of source cores; wherein the input cascade connection is programmable to enable a selected one of the plurality of inputs; wherein the first DPE includes an output cascade connection coupled to a cascade output of the first core and to each of a plurality of target cores of the plurality of DPEs; and wherein the output cascade connection includes a plurality of outputs, wherein each of the plurality of outputs is coupled to a cascade input of a different one of the plurality of target cores. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the input cascade connection is programmable to disable each of the plurality of inputs. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the first core receives data, via the selected one of the plurality of inputs, from a selected source core of the plurality of source cores. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the input cascade connection comprises: a switch coupled to a cascade input of the first core and the cascade output of each core of the plurality of source cores. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein the input cascade connection comprises: a first-in-first-out memory having an input coupled to an output of the switch and an output coupled to the cascade input of the first core. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein a cascade input of the first core is coupled to an internal register of the first core. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the internal register of the first core is coupled to the cascade output of the first core. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the plurality of DPEs are configured to operate as a plurality clusters, wherein each cluster is functionally isolated from each other cluster and each cluster includes one or more of the plurality of DPEs. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein the output cascade connection is configured to send data to each of the plurality of target cores concurrently. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the output cascade connection is programmable to enable selected ones of the plurality of outputs. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the output cascade connection comprises: a switch coupled to the cascade output of the first core and the cascade input of each core of the plurality of target cores. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the output cascade connection comprises: a first-in-first-out memory having an input coupled to the cascade output of the first core and an output coupled to an input of the switch. ### Claim 13 (depends on 1) The integrated circuit of claim 1, wherein an internal register of the first core is coupled to the cascade output of the first core. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the first core sends data from the internal register of the first core, via one or more of the outputs of the output cascade connection, to an internal register of each selected target core of the plurality of target cores. ### Claim 15 A method, comprising: providing a plurality of data processing engines (DPEs) each including a core configured to perform computations; providing a first DPE of the plurality of DPEs having a first core coupled to an input cascade connection of the first core, wherein the input cascade connection is coupled to a plurality of source cores of the plurality of DPEs; wherein the input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is coupled to a cascade output of a different one of the plurality of source cores; programming the input cascade connection to enable a selected one of the plurality of inputs; and providing an output cascade connection coupled a cascade output of the first core and to each of a plurality of target cores of the plurality of DPEs; wherein the output cascade connection includes a plurality of outputs, wherein each of the plurality of outputs is connected to a cascade input of a different one of the plurality of target cores. ### Claim 16 (depends on 15) The method of claim 15, further comprising: in response to programming the input cascade connection to enable a selected one of the plurality of inputs, receiving data via the selected one of the plurality of inputs from a selected source core of the plurality of source cores. ### Claim 17 (depends on 15) The method of claim 15, wherein the plurality of DPEs are configured to operate as a plurality clusters, wherein each cluster is functionally isolated from each other cluster and each cluster includes one or more of the plurality of DPEs. ### Claim 18 (depends on 15) The method of claim 15, further comprising: sending data from the output cascade connection to each of the plurality of target cores concurrently. ### Claim 19 (depends on 15) The method of claim 15, further comprising: programming the output cascade connection to enable selected ones of the plurality of outputs; and concurrently sending data from each of the plurality of outputs of the output cascade connection that is enabled. ### Claim 20 (depends on 15) The method of claim 15, further comprising: sending data from an internal register of the first core, via one or more of the outputs of the output cascade connection, to an internal register of each selected target core of the plurality of target cores.