# US 11,443,089 B1 · Timing verification of non-standard library blocks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,089 B1 - Document ID: US11443089B1 - Status: Granted - Kind: B1 - Application number: 17/249,833 - Filed: 2021-03-15 - Granted: 2022-09-13 - Earliest claimed: 2021-03-15 - Assignees: Amazon Technologies, Inc. - Applicants: Amazon Technologies, Inc. - Inventors: Yuri Geogdjaev - Web page: https://patentgrep.com/patent/US11443089B1 ## CPC - G06F 30/3315: using static timing analysis [STA] - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/3312: Timing analysis - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract To check the timing of a signal path involving an integrated circuit block from an outside vendor, a signal path including a driver circuit, an interconnect, and a receiver circuit can be identified in the integrated circuit design. A substitute integrated circuit design can be generated by replacing the driver circuit of the signal path with a primitive standard library cell, providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool, and replacing the receiver circuit with one or more capacitors. A static timing analysis tool can then be executed on the substitute integrated circuit design to determine whether a propagation delay from the driver circuit to the receiver circuit of the signal path satisfies a timing requirement of the integrated circuit design. ## Claims ### Claim 1 A method comprising: obtaining a transistor level extraction model of an integrated circuit block; incorporating the integrated circuit block into an integrated circuit design; identifying a signal path in the integrated circuit design having a component in the integrated circuit block, the signal path including a driver circuit, an interconnect, and a receiver circuit; generating a substitute integrated circuit design by: replacing the driver circuit of the signal path with a primitive standard library cell of a standard library of the integrated circuit design; replacing the receiver circuit with one or more capacitors; and translating parasitic parameters of the interconnect in the transistor level extraction model into a format for a static timing analysis tool; and executing the static timing analysis tool on the substitute integrated circuit design to determine whether a propagation delay from the driver circuit to the receiver circuit of the signal path satisfies a timing requirement of the integrated circuit design. ### Claim 2 (depends on 1) The method of claim 1, wherein the primitive standard library cell is one of a buffer, an inverter, a NAND gate, or a NOR gate of the standard library. ### Claim 3 (depends on 1) The method of claim 1, wherein translating the parasitic parameters includes translating the parasitic parameters from a Detailed Standard Parasitic Format (DSPF) to a Standard Parasitic Exchange Format (SPEF). ### Claim 4 (depends on 1) The method of claim 1, wherein replacing the receiver circuit includes replacing a plurality of transistors of the receiver circuit that have a transistor gate being driven by the interconnect, each of the plurality of transistors being replaced with a corresponding equivalent capacitor. ### Claim 5 A method comprising: identifying a signal path in an integrated circuit design, the signal path including a driver circuit, an interconnect, and a receiver circuit; generating a substitute integrated circuit design by: replacing the driver circuit of the signal path with a primitive standard library cell; providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool; and replacing the receiver circuit with one or more capacitors; and executing the static timing analysis tool on the substitute integrated circuit design to determine whether a propagation delay from the driver circuit to the receiver circuit of the signal path satisfies a timing requirement of the integrated circuit design. ### Claim 6 (depends on 5) The method of claim 5, wherein the driver circuit is part of an integrated circuit block represented as a transistor level extraction model generated from a schematic netlist. ### Claim 7 (depends on 6) The method of claim 6, wherein the schematic netlist is in a Simulation Program with Integrated Circuit Emphasis (SPICE) format. ### Claim 8 (depends on 5) The method of claim 5, wherein the primitive standard library cell is a buffer, an inverter, a NAND gate, or a NOR gate of a standard library. ### Claim 9 (depends on 5) The method of claim 5, further comprising selecting, from a standard library, the primitive standard library cell having a same drive strength as the driver circuit. ### Claim 10 (depends on 5) The method of claim 5, further comprising selecting, from a standard library, the primitive standard library cell having a closest drive strength to the driver circuit. ### Claim 11 (depends on 5) The method of claim 5, further comprising selecting, from a standard library, the primitive standard library cell having a closest drive strength that is less than a drive strength of the driver circuit. ### Claim 12 (depends on 5) The method of claim 5, wherein the parasitic parameters include a resistance and a capacitance of the interconnect. ### Claim 13 (depends on 5) The method of claim 5, wherein providing the parasitic parameters of the interconnect includes translating the parasitic parameters from a transistor level extraction model to the format compatible with the static timing analysis tool. ### Claim 14 (depends on 13) The method of claim 13, wherein translating the parasitic parameters includes translating the parasitic parameters from a Detailed Standard Parasitic Format (DSPF) to a Standard Parasitic Exchange Format (SPEF). ### Claim 15 (depends on 5) The method of claim 5, wherein the receiver circuit is part of an integrated circuit block represented as a transistor level extraction model generated from a schematic netlist. ### Claim 16 (depends on 15) The method of claim 15, further comprising: for each transistor of the receiver circuit having a transistor gate driven by the interconnect, determining an equivalent capacitance of the transistor. ### Claim 17 (depends on 16) The method of claim 16, wherein determining the equivalent capacitance of each transistor includes executing a standard library characterization tool on each transistor individually. ### Claim 18 A non-transitory computer-readable medium storing code which, when executed by one or more processors, causes the one or more processors to perform operations including: identifying a signal path in an integrated circuit design, the signal path including a driver circuit, an interconnect, and a receiver circuit; generating a substitute integrated circuit design by: replacing the driver circuit of the signal path with a primitive standard library cell of a standard library having a closest drive strength as the driver circuit; providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool; and replacing a transistor of the receiver circuit with a capacitor having an equivalent capacitance; and executing the static timing analysis tool on the substitute integrated circuit design to determine whether the signal path contains a timing violation. ### Claim 19 (depends on 18) The non-transitory computer-readable medium of claim 18, wherein at least one of the driver circuit or the receiver circuit is part of an integrated circuit block represented as a transistor level extraction model generated from a schematic netlist. ### Claim 20 (depends on 18) The non-transitory computer-readable medium of claim 18, wherein providing the parasitic parameters includes translating the parasitic parameters from a Detailed Standard Parasitic Format (DSPF) to a Standard Parasitic Exchange Format (SPEF).