# US 11,443,071 B2 · Secure debug architecture

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- Number: US 11,443,071 B2
- Document ID: US11443071B2
- Status: Granted
- Kind: B2
- Application number: 16/790,222
- Filed: 2020-02-13
- Published: 2021-08-19
- Granted: 2022-09-13
- Earliest claimed: 2020-02-13
- Assignees: SiFive, Inc.
- Applicants: SiFive, Inc.
- Inventors: Yann Loisel; Frank Lhermet
- Web page: https://patentgrep.com/patent/US11443071B2

## CPC

- G06F 21/44: Program or device authentication
- G06F 21/72: in cryptographic circuits
- G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)}
- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G06F 21/572: {Secure firmware programming, e.g. of basic input output system [BIOS]}
- G06F 21/606: {by securing the transmission between two devices or processes}
- G06F 21/73: by creating or determining hardware identification, e.g. serial numbers
- G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices
- H04L 9/0662: {with particular pseudorandom sequence generator}
- H04L 9/0819: {Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) (network architectures or network communication protocols for key distribution in a packet data network H04L63/062)}
- H04L 9/0869: {involving random numbers or seeds}
- H04L 9/3226: {using a predetermined code, e.g. password, passphrase or PIN (network architectures or network communication protocols for supporting authentication of entities using passwords in a packet data network H04L63/083)}
- G06F 2221/033: Test or assess software
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Systems and methods are disclosed for secure debug architecture. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions; a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors; and wherein the integrated circuit is configured to: receive a request from a host device for access to the integrated circuit via the debug interface; responsive to the request, generate a random number; transmit the random number from the integrated circuit to the host device via the debug interface; receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key; and decrypt the input data using the random number as a key.

## Claims

### Claim 1

An integrated circuit for executing instructions comprising:
a processor core configured to execute instructions;
a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors, wherein the debug interface includes an authorization register that is updated to enable or disable the connection between the debug interface and the processor core;
an authentication circuit comprising an authenticated register; and
wherein the integrated circuit is configured to:
receive a request from a host device for access to the integrated circuit via the debug interface;
responsive to the request, generate a random number;
transmit the random number from the integrated circuit to the host device via the debug interface;
receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key, wherein the input data includes at least one of a debug command and a firmware image;
decrypt the input data using the random number as a key: and
update content of the authenticated register based on comparison of the input data to a value stored in non-volatile memory of the integrated circuit, wherein the authentication circuit is configured to update content of the authorization register based on the content of the authenticated register.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, in which the authentication circuit is configured to:
compare an identifier received via the debug interface to an identifier of the integrated circuit that is stored in non-volatile memory of the integrated circuit; and
responsive to the received identifier matching the identifier of the integrated circuit, updating a register to indicate the match and cause the random number to be generated and transmitted.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, in which the authentication circuit is configured to:
compare a portion of the input data to a value stored in non-volatile memory of the integrated circuit; and
responsive to a match between the portion of the input data and the value, enable the debug interface to provide access to the processor core.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, in which the value is a part number or a serial number of the integrated circuit.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, in which the integrated circuit is configured to:
encrypt output data using the random number as a key; and
transmit the encrypted output data to the host device via the debug interface.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, in which the integrated circuit is configured to:
encrypt the random number to obtain an encrypted random number; and
transmit the encrypted random number to the host device via the debug interface.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, in which the random number is encrypted for transmission using a public key stored in the integrated circuit that corresponds to a private key stored by the host device that can be used to decrypt the encrypted random number.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, in which the input data includes signed data that has been signed using a signing key.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, in which the input data includes debug commands for the processor core.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, in which the input data includes a firmware image.

### Claim 11

A method comprising:
receiving a request from a host device for access to an integrated circuit via a debug interface of the integrated circuit;
responsive to the request, generating a random number using the integrated circuit;
transmitting the random number from the integrated circuit to the host device via the debug interface;
receiving, from the host device via the debug interface, input data that has been encrypted using the random number as a key, wherein the input data includes at least one of a debug command and a firmware image;
decrypting the input data, within the integrated circuit, using the random number as a key; and
update content of an authenticated register in an authentication circuit based on comparison of the input data to a value stored in non-volatile memory of the integrated circuit, wherein the authentication circuit is configured to update content of an authorization register in the debug interface based on the content of the authenticated register.

### Claim 12 (depends on 11)

The method of claim 11, comprising:
encrypting output data, within the integrated circuit, using the random number as a key; and
transmitting the encrypted output data to the host device via the debug interface.

### Claim 13 (depends on 11)

The method of claim 11, in which the request is received from the host device via a debug probe connecting the host device to the debug interface of the integrated circuit.

### Claim 14 (depends on 11)

The method of claim 11, in which transmitting the random number from the integrated circuit to the host device via the debug interface comprises:
encrypting the random number using the integrated circuit to obtain an encrypted random number; and
transmitting the encrypted random number from the integrated circuit to the host device via the debug interface.

### Claim 15 (depends on 14)

The method of claim 14, in which the random number is encrypted for transmission using a public key stored in the integrated circuit that corresponds to a private key stored by the host device that can be used to decrypt the encrypted random number.

### Claim 16 (depends on 11)

The method of claim 11, in which the input data includes signed data that has been signed using a signing key.

### Claim 17 (depends on 16)

The method of claim 16, comprising:
comparing an identifier in the request to an identifier of the integrated circuit that is stored in non-volatile memory of the integrated circuit; and
responsive to the identifier in the request matching the identifier of the integrated circuit, updating a register to indicate the match and cause the random number to be generated and transmitted.

### Claim 18

A method comprising:
transmitting a request from a host device for access to an integrated circuit via a debug interface of the integrated circuit;
receiving, using the host device, a random number from the integrated circuit via the debug interface;
encrypting, on the host device, input data using the random number as a key, wherein the input data includes at least one of a debug command and a firmware image;
signing data using a signing key to obtain signed data, in which the input data includes the signed data; and
transmitting from the host device to the integrated circuit via the debug interface the encrypted input data.

### Claim 19 (depends on 18)

The method of claim 18, comprising:
receiving, on the host device, output data from the integrated circuit via the debug interface; and
decrypting, on the host device, the output data using the random number as a key.

### Claim 20 (depends on 18)

The method of claim 18, in which the request is transmitted via a debug probe connecting the host device to the debug interface of the integrated circuit.

### Claim 21 (depends on 18)

The method of claim 18, in which receiving the random number from the integrated circuit via the debug interface comprises:
receiving an encrypted random number from the integrated circuit via the debug interface; and
decrypting the encrypted random number to obtain the random number.

### Claim 22 (depends on 21)

The method of claim 21, in which the encrypted random number is decrypted using a private key stored in the host device that corresponds to a public key stored by the integrated circuit that was used to encrypt the random number.

### Claim 23 (depends on 18)

The method of claim 18, wherein the signing key is an ECDSA (Elliptic Curve Digital Signature Algorithm) key.