# US 11,443,044 B2 · Targeted very long delay for increasing speculative execution progression > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,044 B2 - Document ID: US11443044B2 - Status: Granted - Kind: B2 - Application number: 16/578,741 - Filed: 2019-09-23 - Published: 2021-03-25 - Granted: 2022-09-13 - Earliest claimed: 2019-09-23 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Olaf Knute Hendrickson; Michael P Mullen; Matthew Michael Garcia Pardini - Web page: https://patentgrep.com/patent/US11443044B2 ## CPC - G06F 21/577: {Assessing vulnerabilities and evaluating computer system security} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/3842: {Speculative instruction execution} - G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F 2221/034: Test or assess a computer or a system - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer-implemented method for advancing speculative execution in microarchitectures is disclosed. A non-limiting example of the computer-implemented method includes receiving, by a processor, a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory following the first load instruction. The method executes, by the processor, the first load instruction from the first memory location and delays a return of data from the first memory location for a number of processor cycles. The method executes, by the processor, the speculative storage access instruction from the second memory location during the delay in returning the data from the first memory location. ## Claims ### Claim 1 A computer-implemented method comprising: receiving, by a processor, a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory location following the first load instruction, wherein the speculative memory access instruction is dependent, either directly or indirectly, on information returned by the first load instruction from the first memory location; executing, by the processor, the first load instruction from the first memory location and delaying a return of data from the first memory location for a number of processor cycles; and during the delay in returning data from the first memory location, speculatively executing additional instructions in the test scenario, the speculatively executing comprising: executing, by the processor, the speculative memory access instruction from the second memory location. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, further comprising blocking preloading from the first memory location into a cache. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, wherein the speculative memory access instruction generates an exception. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, wherein the speculative memory access instruction is on a branch not taken path where the branch decision is dependent on information from the first load instruction from the first memory location. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, wherein the speculative memory access instruction immediately follows the first load instruction. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, wherein the number of processor cycles is greater than 1000 cycles. ### Claim 7 (depends on 1) The computer-implemented method of claim 1, further comprising detecting a security leak during execution of instructions on a speculative path following the speculative memory access instruction by scanning for an observable change to microarchitected results of the test scenario. ### Claim 8 A system comprising: a processor, memory coupled to the processor, the memory having stored therein instructions that when executed cause the processor to: receive a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory location following the first load instruction, wherein the speculative memory access instruction is dependent, either directly or indirectly, on information returned by the first load instruction from the first memory location; execute the first load instruction from the first memory location and delaying a return of data from the first memory location for a number of processor cycles; and during the delay in returning data from the first memory location, speculatively execute additional instructions in the test scenario, the speculatively executing comprising: executing the speculative memory access instruction from the second memory location. ### Claim 9 (depends on 8) The system of claim 8, further comprising instructions that cause the processor to block preloading from the first memory location into a cache. ### Claim 10 (depends on 8) The system of claim 8, wherein the speculative memory access instruction generates an exception. ### Claim 11 (depends on 8) The system of claim 8, wherein the speculative memory access instruction is on a branch not taken path where the branch decision is dependent on information from the first load instruction from the first memory location. ### Claim 12 (depends on 8) The system of claim 8, wherein the speculative memory access instruction immediately follows the first load instruction. ### Claim 13 (depends on 8) The system of claim 8, wherein the number of processor cycles is greater than 1000 cycles. ### Claim 14 (depends on 8) The system of claim 8, wherein the instruction when executed further causes the processor to detect a security leak during execution of instructions on a speculative path following the speculative memory access instruction by scanning for an observable change to microarchitected results of the test scenario. ### Claim 15 A computer program product for advancing speculative execution in microarchitectures, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: receive a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory location following the first load instruction, wherein the speculative memory access instruction is dependent, either directly or indirectly, on information returned by the first load instruction from the first memory location; execute the first load instruction from the first memory location and delaying a return of data from the first memory location for a number of processor cycles; and during the delay in returning data from the first memory location, speculatively execute additional instructions in the test scenario, the speculatively executing comprising: executing the speculative memory access instruction from the second memory location. ### Claim 16 (depends on 15) The computer program product of claim 15, further comprising instructions that cause the processor to block preloading from the first memory location into a cache. ### Claim 17 (depends on 15) The computer program product of claim 15, wherein the speculative memory access instruction generates an exception. ### Claim 18 (depends on 15) The computer program product of claim 15, wherein the speculative memory access instruction is on a branch not taken path where the branch decision is dependent on information from the first load instruction from the first memory location. ### Claim 19 (depends on 15) The computer program product of claim 15, wherein the speculative memory access instruction immediately follows the first load instruction. ### Claim 20 (depends on 15) The computer program product of claim 15, further comprising detecting a security leak during execution of instructions on a speculative path following the speculative memory access instruction by scanning for an observable change to microarchitected results of the test scenario.