# US 11,442,889 B2 · Dynamic deep learning processor architecture

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- Number: US 11,442,889 B2
- Document ID: US11442889B2
- Status: Granted
- Kind: B2
- Application number: 16/146,886
- Filed: 2018-09-28
- Published: 2019-02-07
- Granted: 2022-09-13
- Earliest claimed: 2018-09-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Eriko Nurvitadhi; Scott J. Weber; Ravi Prakash Gutala; Aravind Raghavendra Dasu
- Web page: https://patentgrep.com/patent/US11442889B2

## CPC

- G06F 15/76: Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16)
- G06F 15/7867: {with reconfigurable architecture}
- G06F 15/8046: {Systolic arrays}
- G06N 3/0495: Quantised networks; Sparse networks; Compressed networks
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G06N 3/082: modifying the architecture, e.g. adding, deleting or silencing nodes or connections
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses}
- H10W 90/00: Package configurations
- G06F 2015/768: {Gate array}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.

## Claims

### Claim 1

An integrated circuit device comprising:
a deep learning processor comprising:
a matrix execution circuitry that couples to and configures one or more processing elements of a programmable fabric, wherein the matrix execution circuitry comprises configuration memory to store configurations and to load the configurations as configuring the one or more processing elements; and
an instruction-based controller configured to:
monitor one or more parameters of a deep learning algorithm implemented in the deep learning processor, wherein the one or more parameters comprises sparsity of data analyzed b the deep learning processor; and
based at least in part on the one or more monitored parameters, reconfigure the one or more processing elements to increase efficiency of the deep learning processor.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the deep learning processor is implemented in a programmable logic device.

### Claim 3 (depends on 2)

The integrated circuit device of claim 2, wherein the programmable logic device comprises a programmable fabric that includes the one or more processing elements.

### Claim 4 (depends on 3)

The integrated circuit device of claim 3, wherein reconfiguring the one or more processing elements comprises partially reconfiguring the programmable fabric at runtime without reconfiguring the entire programmable fabric.

### Claim 5 (depends on 2)

The integrated circuit device of claim 2, wherein the programmable logic device comprises a field-programmable gate array.

### Claim 6 (depends on 1)

The integrated circuit device of claim 1, wherein the deep learning processor comprises an external data management sub-system that controls an interface with an external device external to the integrated circuit device using a programmable fabric.

### Claim 7 (depends on 6)

The integrated circuit device of claim 6, wherein the instruction-based controller configures the interface via the external data management sub-system to include to compress transmissions to the external device.

### Claim 8 (depends on 6)

The integrated circuit device of claim 6, wherein the instruction-based controller configures the interface via the external data management sub-system to include to cryptographically secure transmissions to the external device.

### Claim 9 (depends on 1)

The integrated circuit device of claim 1, wherein reconfiguring the one or more processing elements comprises reconfiguring connections between the one or more processing elements.

### Claim 10 (depends on 1)

The integrated circuit device of claim 1, wherein reconfiguring the one or more processing elements comprises internal portions of the processing elements.

### Claim 11 (depends on 10)

The integrated circuit device of claim 10, wherein reconfiguring the one or more processing elements comprises selecting an engine between a standard dot product engine and a standardized dot product engine and configuring the one or more processing elements with the selected engine.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, wherein when the data analyzed comprises a sparse matrix, reconfiguring the one or more processing elements—includes sparse support circuitry of the one or more processing elements that compresses the sparse matrix for processing by one or more processing elements.

### Claim 13

A method comprising:
operating deep learning processor using a first configuration;
tracking one or more parameters of a deep learning program using the deep learning processor in the first configuration, wherein the one or more parameters comprises sparsity of data analyzed by the deep learning processor; and
reconfiguring one or more processing elements of a programmable fabric of the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.

### Claim 14 (depends on 13)

The method of claim 13, wherein tracking the one or more parameters comprises latency of the deep learning processor.

### Claim 15 (depends on 14)

The method of claim 14, wherein reconfiguring the deep learning processor comprises reconfiguring the deep learning processor to decrease latency when the latency has exceeded a threshold by reconfiguring the deep learning processor to arrange a broadcast configuration of one or more processing elements in a parallel configuration.

### Claim 16 (depends on 14)

The method of claim 14, wherein the one or more parameters comprises a stall in execution of the deep learning program, and reconfiguring the deep learning processor comprises reconfiguring the deep learning processor to increase throughput when throughput has dropped below a threshold by reconfiguring the deep learning processor to arrange a two-dimensional systolic configuration of one or more processing elements.

### Claim 17

Tangible, non-transitory, and computer-readable medium having instructions stored thereon instructions, that when executed, are configured to cause a deep learning processor to:
configure the deep learning processor in a first configuration;
operate the deep learning processor using the first configuration;
track one or more parameters of a deep learning program using the deep learning processor in the first configuration, wherein the one or more parameters comprises sparsity of data analyzed by the deep learning processor; and
based on the one or more tracked parameters, reconfigure one or more processing elements of a programmable fabric to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program.

### Claim 18 (depends on 17)

The tangible, non-transitory, and computer-readable medium of claim 17, wherein the deep learning processor comprises a multi-function sub-system that controls configuration of multiple functions in the one or more processing elements, wherein a first configuration comprises a series different functions implemented in the one or more processing elements, and a second configuration comprises parallel execution of a single function in the one or more processing elements.