# US 11,442,888 B2 · Serial communication apparatus for unidirectional communication between chips of radio frequency front-end module and inside the chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,888 B2 - Document ID: US11442888B2 - Status: Granted - Kind: B2 - Application number: 17/138,530 - Filed: 2020-12-30 - Published: 2021-04-22 - Granted: 2022-09-13 - Earliest claimed: 2019-06-28 - Assignees: Vanchip (Tianjin) Technology Co., Ltd. - Applicants: Qihua Zhang; Yunfang Bai - Inventors: Qihua Zhang; Yunfang Bai - Web page: https://patentgrep.com/patent/US11442888B2 ## CPC - G06F 13/4291: {using a clocked protocol} - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - H04B 1/40: Circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04B: TRANSMISSION ## Abstract Disclosed are a serial communication apparatus and a serial communication method. The serial communication apparatus comprises a radio frequency front-end module and a radio frequency device, a first input interface and a second input interface of the radio frequency front-end module being correspondingly connected to output interfaces of a main control module, a first output interface of the radio frequency front-end module being connected to a first input interface of the at least one radio frequency device via a first signal bus, a second output interface of the radio frequency front-end module being connected to a second input interface of the at least one radio frequency device via a second signal bus. The present invention satisfies requirements for convenient and rapid unidirectional communication between various chips of the radio frequency front-end module and inside the chips, reduces communication complexity, and increases transmission efficiency. ## Claims ### Claim 1 A serial communication apparatus, comprising a radio frequency front-end module and radio frequency devices, wherein a first input interface and a second input interface of the radio frequency front-end module are respectively connected to output interfaces of a main control module, and when a first output interface of the radio frequency front-end module is connected to a first input interface of at least one of the radio frequency devices via a first signal bus, a second output interface of the radio frequency front-end module is connected to a second input interface of the at least one of the radio frequency devices via a second signal bus; when valid SIPI data received by each of the radio frequency devices contains a clock signal, the radio frequency device comprises a second power-on reset circuit and a receiving circuit, wherein the second power-on reset circuit is connected to the receiving circuit, and when a first input interface of the receiving circuit is connected to a first output interface of a transmission circuit via the first signal bus, a second input interface of the receiving circuit is connected to a second output interface of the transmission circuit via the second signal bus, or the second input interface of the receiving circuit is connected to a corresponding second output interface of the transmission circuit via the second signal bus. ### Claim 2 (depends on 1) The serial communication apparatus according to claim 1, wherein the radio frequency front-end module comprises a first detection circuit, a first clock generation circuit, and a transmission circuit, wherein a first input interface and a second input interface of the first detection circuit are respectively connected to the output interfaces of the main control module, the first detection circuit is connected to an input interface of the first clock generation circuit via one or more clock enable buses, an output interface of the first clock generation circuit is connected to a first input interface of the transmission circuit, and an output interface of the first detection circuit is connected to a second input interface of the transmission circuit. ### Claim 3 (depends on 2) The serial communication apparatus according to claim 2, wherein the radio frequency front-end module further comprises a first power-on reset circuit, wherein the first power-on reset circuit is connected to the transmission circuit. ### Claim 4 (depends on 1) The serial communication apparatus according to claim 1, wherein when valid SIPI data received by each of the radio frequency devices does not contain a clock signal, the radio frequency device comprises a second power-on reset circuit, a receiving circuit, and a second clock generation circuit, wherein the second power-on reset circuit is connected to the receiving circuit, an output interface of the receiving circuit is connected to an input interface of the second clock generation circuit via one or more clock enable buses, an output interface of the second clock generation circuit is connected to an input interface of the receiving circuit, and when a first input interface of the receiving circuit is connected to a first output interface of a transmission circuit via the first signal bus, a second input interface of the receiving circuit is connected to a second output interface of the transmission circuit via the second signal bus, or the second input interface of the receiving circuit is connected to a corresponding second output interface of the transmission circuit via the second signal bus. ### Claim 5 A serial communication apparatus, comprising a radio frequency front-end module and radio frequency devices, wherein a first input interface and a second input interface of the radio frequency front-end module are respectively connected to output interfaces of a main control module, at least one first output interface of the radio frequency front-end module is connected to a first input interface of at least one of the radio frequency devices via a first signal bus, and at least one second output interface of the radio frequency front-end module is connected to a second input interface of the at least one of the radio frequency devices via a second signal bus; when valid SIPI data received by each of the radio frequency devices contains a clock signal, the radio frequency device comprises a second power-on reset circuit and a receiving circuit, wherein the second power-on reset circuit is connected to the receiving circuit, a first input interface of the receiving circuit is connected to a corresponding first output interface of a transmission circuit via the first signal bus, and a second input interface of the receiving circuit is connected to a corresponding second output interface of the transmission circuit via the second signal bus. ### Claim 6 (depends on 5) The serial communication apparatus according to claim 5, wherein when valid SIPI data received by each of the radio frequency devices does not contain a clock signal, the radio frequency device comprises a second power-on reset circuit, a receiving circuit, and a second clock generation circuit, wherein the second power-on reset circuit is connected to the receiving circuit, an output interface of the receiving circuit is connected to an input interface of the second clock generation circuit via one or more clock enable buses, an output interface of the second clock generation circuit is connected to an input interface of the receiving circuit, a first input interface of the receiving circuit is connected to a corresponding first output interface of a transmission circuit via the first signal bus, and a second input interface of the receiving circuit is connected to a corresponding second output interface of the transmission circuit via the second signal bus. ### Claim 7 (depends on 5) The serial communication apparatus according to claim 5, wherein the radio frequency front-end module comprises a first detection circuit, a first clock generation circuit, and a transmission circuit, wherein a first input interface and a second input interface of the first detection circuit are respectively connected to the output interfaces of the main control module, the first detection circuit is connected to an input interface of the first clock generation circuit via one or more clock enable buses, an output interface of the first clock generation circuit is connected to a first input interface of the transmission circuit, and an output interface of the first detection circuit is connected to a second input interface of the transmission circuit. ### Claim 8 (depends on 7) The serial communication apparatus according to claim 7, wherein the radio frequency front-end module further comprises a first power-on reset circuit, wherein the first power-on reset circuit is connected to the transmission circuit. ### Claim 9 A serial communication apparatus, comprising a radio frequency front-end module and radio frequency devices, wherein a first input interface and a second input interface of the radio frequency front-end module are respectively connected to output interfaces of a main control module, a first output interface of the radio frequency front-end module is connected to a first input interface of a first one of the radio frequency devices via a first signal bus, a second output interface of the radio frequency front-end module is connected to a second input interface of the first one of the radio frequency devices via a second signal bus, and starting from the first one of the radio frequency devices, the radio frequency devices are successively connected via the first signal bus and the second signal bus respectively; when valid SIPI data received by each of the radio frequency devices contains a clock signal, the radio frequency device comprises a second power-on reset circuit and a receiving circuit, wherein the second power-on reset circuit is connected to the receiving circuit, a first input interface of the receiving circuit of the first one of the radio frequency devices is connected to a first output interface of a transmission circuit via the first signal bus, a second input interface of the receiving circuit of the first one of the radio frequency devices is connected to a second output interface of the transmission circuit via the second signal bus, and starting from the first one of the radio frequency devices, the receiving circuits of the radio frequency devices are successively connected via the first signal bus and the second signal bus respectively. ### Claim 10 (depends on 9) The serial communication apparatus according to claim 9, wherein when valid SIPI data received by each of the radio frequency devices does not contain a clock signal, the radio frequency device comprises a second power-on reset circuit, a receiving circuit, and a second clock generation circuit, wherein the second power-on reset circuit is connected to the receiving circuit, an output interface of the receiving circuit is connected to an input interface of the second clock generation circuit via one or more clock enable buses, an output interface of the second clock generation circuit is connected to an input interface of the receiving circuit, a first input interface of the receiving circuit of the first one of the radio frequency devices is connected to a first output interface of a transmission circuit via the first signal bus, a second input interface of the receiving circuit of the first one of the radio frequency devices is connected to a second output interface of the transmission circuit via the second signal bus, and starting from the first one of the radio frequency device, the receiving circuits of the radio frequency devices are successively connected via the first signal bus and the second signal bus respectively. ### Claim 11 (depends on 9) The serial communication apparatus according to claim 9, wherein the radio frequency front-end module comprises a first detection circuit, a first clock generation circuit, and a transmission circuit, wherein a first input interface and a second input interface of the first detection circuit are respectively connected to the output interfaces of the main control module, the first detection circuit is connected to an input interface of the first clock generation circuit via one or more clock enable buses, an output interface of the first clock generation circuit is connected to a first input interface of the transmission circuit, and an output interface of the first detection circuit is connected to a second input interface of the transmission circuit. ### Claim 12 (depends on 11) The serial communication apparatus according to claim 11, wherein the radio frequency front-end module further comprises a first power-on reset circuit, wherein the first power-on reset circuit is connected to the transmission circuit.