# US 11,442,885 B2 · System and method to change field-programmable gate array personality from a baseboard management controller

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- Number: US 11,442,885 B2
- Document ID: US11442885B2
- Status: Granted
- Kind: B2
- Application number: 16/537,097
- Filed: 2019-08-09
- Published: 2021-02-11
- Granted: 2022-09-13
- Earliest claimed: 2019-08-09
- Assignees: Dell Products L.P.
- Applicants: Dell Products, LP
- Inventors: Johan Rahardjo; Isaac Qin Wang; Elie Antoun Jreij; Akkiah Choudary Maddukuri; Rama Rao Bisa; Pavan Kumar Gavvala
- Web page: https://patentgrep.com/patent/US11442885B2

## CPC

- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)}
- G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)}
- G06F 13/20: for access to input/output bus
- G06F 2213/0016: Inter-integrated circuit (I2C)
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA and a card BMC. The FPGA is programmed with a plurality of accelerated function units (AFUs) to perform processing tasks for the processor. The card BMC receives a first indication from the system BMC, the first indication to halt a first processing task associated with a first AFU, halts the first processing task in response to the first indication, receives a second AFU from the system BMC, and reprograms the FPGA with the second AFU.

## Claims

### Claim 1

An information handling system, comprising:
a processor;
a system baseboard management controller (BMC); and
a field-programmable gate array (FPGA) add-in card, including:
an FPGA configured to be programmed with a plurality of accelerated function units (AFUs), the AFUs to perform processing tasks for the processor; and
a card BMC configured to:
receive a first indication from the system BMC, the first indication to halt a first processing task associated with a first AFU;
halt the first processing task in response to the first indication;
receive a second AFU from the system BMC; and
reprogram the FPGA with the second AFU.

### Claim 2 (depends on 1)

The information handling system of claim 1, wherein, prior to sending the first indication to the card BMC, the system BMC is configured to:
receive a second indication from the processor that the first processing task is complete, wherein the first indication is sent in response to the second indication.

### Claim 3 (depends on 1)

The information handling system of claim 1, the FPGA add-in card further comprising:
a first communication interface configured to couple the FPGA to a processor of the information handling system, the FPGA to transfer data associated with the processing tasks performed by the AFUs via the first communication interface.

### Claim 4 (depends on 3)

The information handling system of claim 3, wherein the FPGA add-in card is configured to:
receive a second indication from the processor via the first communication interface, the second indication to halt a second processing task associated with the second AFU;
halt the second processing task in response to the second indication;
receive a third AFU from the processor via the first communication interface; and
reprogram the FPGA with the third AFU.

### Claim 5 (depends on 3)

The information handling system of claim 3, wherein the first communication interface includes a Peripheral Component Interconnect-Express (PCIe) interface.

### Claim 6 (depends on 3)

The information handling system of claim 3, the FPGA add-in card further comprising:
a second communication interface configured to couple the card BMC to the system BMC.

### Claim 7 (depends on 6)

The information handling system of claim 6, wherein the card BMC receives the first indication and the second AFU from the system BMC via the second interface.

### Claim 8 (depends on 6)

The information handling system of claim 6, wherein the second communication interface includes an Inter-Integrated Circuit (I2C) interface.

### Claim 9

A field-programmable gate array (FPGA) add-in card, comprising:
an FPGA configured to be programmed with a plurality of accelerated function units (AFUs), the AFUs to perform processing tasks for an information handling system into which the FPGA add-in card may be installed; and
a card baseboard management controller (BMC) configured to:
receive a first indication from a system BMC, the first indication to halt a first processing task associated with a first AFU;
halt the first processing task in response to the first indication;
receive a second AFU from the system BMC; and
reprogram the FPGA with the second AFU.

### Claim 10 (depends on 9)

The FPGA add-in card of claim 9, further comprising:
a first communication interface configured to couple the FPGA to a processor of the information handling system, the FPGA to transfer data associated with the processing tasks performed by the AFUs via the first communication interface.

### Claim 11 (depends on 10)

The FPGA add-in card of claim 10, configured to:
receive a second indication from the processor via the first communication interface, the second indication to halt a second processing task associated with the second AFU;
halt the second processing task in response to the second indication;
receive a third AFU from the processor via the first communication interface; and
reprogram the FPGA with the third AFU.

### Claim 12 (depends on 10)

The FPGA add-in card of claim 10, wherein the first communication interface includes a Peripheral Component Interconnect-Express (PCIe) interface.

### Claim 13 (depends on 10)

The FPGA add-in card of claim 10, further comprising:
a second communication interface configured to couple the card BMC to the system BMC.

### Claim 14 (depends on 13)

The FPGA add-in card of claim 13, wherein the card BMC receives the first indication and the second AFU from the system BMC via the second interface.

### Claim 15 (depends on 13)

The FPGA add-in card of claim 13, wherein the second communication interface includes an Inter-Integrated Circuit (I2C) interface.

### Claim 16

A method of programming a field-programmable gate array (FPGA) of an add-in card with a plurality of accelerated function units (AFUs), the AFUs to perform processing tasks for an information handling system into which the add-in card is installed, the method comprising:
receiving, by a card baseboard management controller (BMC) of the add-in card, a first indication from a system BMC of the information handling system, the first indication to halt a first processing task associated with a first AFU;
halting, by the card BMC, the first processing task in response to the first indication;
receiving, by the card BMC, a second AFU from the system BMC; and
reprogramming, by the card BMC, the FPGA with the second AFU.

### Claim 17 (depends on 16)

The method of claim 16, configured to:
receiving, via a first communication interface configured to couple the FPGA to a processor of the information handling system, a second indication from the processor, the second indication to halt a second processing task associated with the second AFU;
halting the second processing task in response to the second indication;
receiving, via the first communication interface, a third AFU from the processor; and
reprogramming the FPGA with the third AFU.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first communication interface includes a Peripheral Component Interconnect-Express (PCIe) interface.

### Claim 19 (depends on 16)

The method of claim 16, wherein the card BMC receives the first indication and the second AFU from the system BMC via a second interface.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second communication interface includes an Inter-Integrated Circuit (I2C) interface.