# US 11,442,882 B2 · Bridge circuit for providing conversion between PCIe-NVMe protocol and NVMe-TCP protocol and computer system using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,882 B2 - Document ID: US11442882B2 - Status: Granted - Kind: B2 - Application number: 17/234,751 - Filed: 2021-04-19 - Published: 2021-11-04 - Granted: 2022-09-13 - Earliest claimed: 2020-05-04 - Assignees: VIA Technologies, Inc. - Applicants: VIA Technologies Inc. - Inventors: Jiin Lai - Web page: https://patentgrep.com/patent/US11442882B2 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 13/1668: {Details of memory controller} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - H04L 69/161: {Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields} - H04L 69/168: specially adapted for link layer protocols, e.g. asynchronous transfer mode [ATM], synchronous optical network [SONET] or point-to-point protocol [PPP] - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host. ## Claims ### Claim 1 A bridge circuit, comprising: a Non-Volatile Memory Express (NVMe) device controller, arranged to communicate with a host via a Peripheral Component Interconnect Express (PCIe) bus; a network subsystem, arranged to communicate with an NVME over Transmission Control Protocol (NVMe-TCP) device via a network; and a data transfer circuit, coupled between the NVMe device controller and the network subsystem, and arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host; wherein data transfer between the host and the NVMe-TCP device is processed according to a set of an NVMe command identifier, a TCP session identifier, and an NVMe-TCP command identifier. ### Claim 2 (depends on 1) The bridge circuit of claim 1, wherein the NVMe device controller comprises: a PCIe controller, arranged to access the PCIe bus; a host controller, coupled to the PCIe controller, and arranged to control upstream transaction and downstream transaction of the PCIe bus, NVMe configuration setting, and PCIe configuration setting; a submission queue processing circuit, coupled to the host controller, and arranged to read and process a command in a submission queue of the host; a completion queue processing circuit, coupled to the host controller, and arranged to write completion information of the command into a completion queue of the host; and a storage address processing circuit, coupled to the host controller, and arranged to retrieve storage address information carried by the command, and configure the data transfer circuit according to the storage address information. ### Claim 3 (depends on 1) The bridge circuit of claim 1, wherein the network subsystem comprises: an offload engine, arranged to process Transmission Control Protocol/Internet Protocol (TCP/IP) stack between the network subsystem and the NVMe-TCP device; and an NVMe-TCP controller, arranged to trigger the data transfer circuit to read data from the host and transmit the data to the NVMe-TCP device via the offload engine, and trigger the data transfer circuit to transmit data received by the offload engine from the NVMe-TCP device to the host. ### Claim 4 (depends on 1) The bridge circuit of claim 1, wherein the data transfer circuit comprises: a first storage element, arranged to store a first linked list, where each node in the first linked list records a storage address in a system storage device of the host; a second storage element, arranged to store a second linked list, where each node in the second linked list records a storage address in a local storage device used by the bridge circuit; a third storage element, arranged to store a lookup table, where the lookup table records a storage address of a first node in the first linked list in the first storage element and a storage address of a first node in the second linked list in the second storage element; and a data access circuit, arranged to read the first linked list and the second linked list according to the lookup table, to process data transfer between the host and the NVMe-TCP device. ### Claim 5 (depends on 4) The bridge circuit of claim 4, wherein the lookup table further records that the set of the NVMe command identifier, the TCP session identifier, and the NVMe-TCP command identifier that is mapped to the storage address of the first node in the first linked list in the first storage element and the storage address of the first node in the second linked list in the second storage element; and the data access circuit is further arranged to read the storage address of the first node in the first linked list in the first storage element and the storage address of the first node in the second linked list in the second storage element from the lookup table according to the set of the NVMe command identifier, the TCP session identifier, and the NVMe-TCP command identifier. ### Claim 6 (depends on 4) The bridge circuit of claim 4, wherein the data access circuit starts to read the first linked list according to the storage address of the first node in the first linked list in the first storage element, to read a data from the system storage device, and starts to read the second linked list according to the storage address of the first node in the second linked list in the second storage element, to write the data into the local storage device. ### Claim 7 (depends on 6) The bridge circuit of claim 6, wherein the data access circuit further starts to read the second linked list according to the storage address of the first node in the second linked list in the second storage element, to read the data from the local storage device, and transmits the data to the NVMe-TCP device via the network subsystem. ### Claim 8 (depends on 4) The bridge circuit of claim 4, wherein the network subsystem receive a data from the NVMe-TCP device; and the data access circuit starts to read the second linked list according to the storage address of the first node in the second linked list in the second storage element, to write the data into the local storage device. ### Claim 9 (depends on 8) The bridge circuit of claim 8, wherein the data access circuit further starts to read the second linked list according to the storage address of the first node in the second linked list in the second storage element, to read the data from the local storage device, and starts to read the first linked list according to the storage address of the first node in the first linked list in the first storage element, to write the data into the system storage device. ### Claim 10 (depends on 1) The bridge circuit of claim 1, wherein the bridge circuit is disposed in a PCIe interface card. ### Claim 11 (depends on 1) The bridge circuit of claim 1, wherein the NVMe device controller, the network subsystem, and the data transfer circuit are all disposed in a same chip. ### Claim 12 A computer system, comprising: a host; and a bridge circuit, comprising: a Non-Volatile Memory Express (NVMe) device controller, arranged to communicate with the host via a Peripheral Component Interconnect Express (PCIe) bus; a network subsystem, arranged to communicate with an NVME over Transmission Control Protocol (NVMe-TCP) device via a network; and a data transfer circuit, coupled between the NVMe device controller and the network subsystem, and arranged to deal with data transfer associated with the NVMe-TCP device; wherein the bridge circuit makes the host regard the NVMe-TCP device as a PCIe-NVMe device for data access, and data transfer between the host and the NVMe-TCP device is processed according to a set of an NVMe command identifier, a TCP session identifier, and an NVMe-TCP command identifier. ### Claim 13 A computer system, comprising: a host; and a bridge circuit, comprising: a Non-Volatile Memory Express (NVMe) device controller, arranged to communicate with the host via a Peripheral Component Interconnect Express (PCIe) bus; a network subsystem, arranged to communicate with an NVME over Transmission Control Protocol (NVMe-TCP) device via a network; and a data transfer circuit, coupled between the NVMe device controller and the network subsystem, and arranged to deal with data transfer associated with the NVMe-TCP device; wherein the host loads and executes a PCIe-NVMe driver to control communication between the host and the NVMe device controller, without being equipped with an NVMe-TCP driver, and data transfer between the host and the NVMe-TCP device is processed according to a set of an NVMe command identifier, a TCP session identifier, and an NVMe-TCP command identifier.