# US 11,442,881 B2 · MAC processing pipelines, circuitry to control and configure same, and methods of operating same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,881 B2 - Document ID: US11442881B2 - Status: Granted - Kind: B2 - Application number: 17/212,411 - Filed: 2021-03-25 - Published: 2021-10-21 - Granted: 2022-09-13 - Earliest claimed: 2020-04-18 - Assignees: Flex Logix Technologies, Inc. - Applicants: Flex Logix Technologies, Inc. - Inventors: Frederick A. Ware; Cheng C. Wang - Web page: https://patentgrep.com/patent/US11442881B2 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit including control/configure circuitry which interfaces with a plurality of interconnected (e.g., serially) multiplier-accumulator circuits and/or one or more rows of interconnected (e.g., serially) multiplier-accumulator circuits. The control/configure circuitry may include a plurality of control/configure circuits, each control/configure circuit interfaces with at least one multi-bit MAC execution pipeline, wherein each pipeline includes a plurality of interconnected (e.g., serially) multiplier-accumulator circuits. Each control/configure circuit may include one or more (or all) of (i) a configurable input data signal path to provide data to the MACs of the pipeline during the execution sequence(s), (ii) a configurable accumulation data path for the ongoing/accumulating MAC accumulation totals generated by the MACs during an execution sequence, and (iii) a configurable output data path for the output data generated by execution sequence (i.e., input data that was processed via the multiplier-accumulator circuits or MAC processors of the execution pipeline). ## Claims ### Claim 1 An integrated circuit comprising: a plurality of multiplier-accumulator circuits organized into a plurality of groups, wherein each group of multiplier-accumulator circuits includes a plurality of multiplier-accumulator circuits that is connected in series to perform a plurality of multiply and accumulate operations, wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of each group includes: a multiplier to multiply data by a multiplier weight data and generate a product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add input data and the product data of the associated multiplier to generate sum data; a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with one of the groups of multiplier-accumulator circuits, wherein each control/configure circuit includes: a plurality of data paths wherein each data path includes: a first end that directly connects to an input of a first multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of the associated group of multiplier-accumulator circuits, a second end that directly connects to an output of a last multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of the associated group of multiplier-accumulator circuits, wherein the first end of the data path couples to the second end of the data path through the plurality of serially connected multiplier-accumulator circuits of the associated group of the plurality of multiplier-accumulator circuits, a third end that is configurable to connect to an end of a corresponding data path of a different one of the plurality of control/configure circuits, and a fourth end; wherein the plurality of data paths of each control/configure circuit includes: a first data path to receive input data to be processed into each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits at a start of an execution sequence. ### Claim 2 (depends on 1) The integrated circuit of claim 1 wherein: the plurality of control/configure circuits includes a first control/configure circuit, a second control/configure circuit and a third control/configure circuit, the third end of the first data path of the first control/configure circuit is configured to connect to the third end of the first data path of the second control/configure circuit, and the fourth end of the first data path of the first control/configure circuit is coupled to a first memory which stores the input data. ### Claim 3 (depends on 2) The integrated circuit of claim 2 wherein: the fourth end of the first data path of the second control/configure circuit is coupled to the third end of the first data path of the third control/configure circuits. ### Claim 4 (depends on 2) The integrated circuit of claim 2 wherein: the plurality of data paths of each control/configure circuit further includes a second data path to output data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier- accumulator circuits at an end of an execution sequence, the third end of the second data path of the first control/configure circuit is configured to connect to the third end of the second data path of the second control/configure circuit, the fourth end of the second data path of the second control/configure circuit is coupled to the third end of the second data path of the third control/configure circuit, and wherein the integrated circuit further includes configurable processing circuitry, coupled to the fourth end of the second data path of the third control/configure circuit to: (i) receive the output data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits and (ii) process the output data wherein the processed output data are stored in the second memory. ### Claim 5 (depends on 4) The integrated circuit of claim 4 wherein: the configurable processing circuitry includes a plurality of configurable data paths and one or more circuits connected therein, wherein the one or more circuits process the output data via addition/subtraction with a register value, multiplication by a register value, conversion from integer data format to floating point data format, conversion from floating point data format to integer data format, adjustment in format precision, and/or monadic function(s) including: inverse, square root, inverse square root, hyperbolic tangent and/or sigmoid. ### Claim 6 (depends on 1) The integrated circuit of claim 1 wherein: the plurality of data paths of each control/configure circuit further includes a third data path to rotate partial accumulation values to each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits during an execution sequence. ### Claim 7 An integrated circuit comprising: a plurality of multiplier-accumulator circuits organized into a plurality of groups, wherein each group of multiplier-accumulator circuits includes a plurality of multiplier-accumulator circuits that is connected in series to perform a plurality of multiply and accumulate operations, wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of each group includes: a multiplier to multiply data by a multiplier weight data and generate a product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add input data and the product data of the associated multiplier to generate sum data; a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with one of the groups of multiplier-accumulator circuits, wherein each control/configure circuit includes: a plurality of data paths wherein each data path includes: a first end that directly connects to an input of a first multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of the associated group of multiplier-accumulator circuits, a second end that directly connects to an output of a last multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of the associated group of multiplier-accumulator circuits, wherein the first end of the data path couples to the second end of the data path through the plurality of serially connected multiplier-accumulator circuits of the associated group of the plurality of multiplier-accumulator circuits, a third end that is configurable to connect to an end of a corresponding data path of a different one of the plurality of control/configure circuits, and a fourth end; wherein the plurality of data paths of each control/configure circuit includes: a first data path to input accumulation values to and output accumulation values from each group of the plurality of multiplier-accumulator circuits during an execution sequence. ### Claim 8 (depends on 7) The integrated circuit of claim 7 wherein: the first data path to input partial accumulation values to and output partial accumulation values from each group of the plurality of multiplier-accumulator circuits during an execution sequence. ### Claim 9 (depends on 7) The integrated circuit of claim 7 wherein: the plurality of control/configure circuits includes a first control/configure circuit, a second control/configure circuit and a third control/configure circuit, the third end of the first data path of the first control/configure circuit is configured to connect to the third end of the first data path of the second control/configure circuit, the fourth end of the first data path of the second control/configure circuit is coupled to the third end of the first data path of the third control/configure circuit, and the fourth end of the first data path of the third control/configure circuit is connected to the fourth end of the first data path of the first control/configure circuit. ### Claim 10 (depends on 9) The integrated circuit of claim 9 wherein: the plurality of control/configure circuits are disposed in a row, and the first control/configure circuit and the third control/configure circuit are located at first and second edges, respectively, of the plurality of control/configure circuits. ### Claim 11 (depends on 9) The integrated circuit of claim 9 wherein: the plurality of data paths of each control/configure circuit further includes a second data path to output data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier- accumulator circuits at an end of an execution sequence, the third end of the second data path of the first control/configure circuit is configured to connect to the third end of the second data path of the second control/configure circuit, the fourth end of the second data path of the first control/configure circuit is coupled to a first memory which stores the output data, and the fourth end of the second data path of the second control/configure circuit is coupled to the third end of the second data path of the third control/configure circuit. ### Claim 12 (depends on 11) The integrated circuit of claim 11 wherein: the fourth end of the second data path of the third control/configure circuit is coupled to the first memory which stores the output data. ### Claim 13 (depends on 9) The integrated circuit of claim 9 wherein: the plurality of data paths of each control/configure circuit includes a second data path to input data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits at an start of an execution sequence the third end of the second data path of the first control/configure circuit is configured to connect to the third end of the second data path of the second control/configure circuit, the fourth end of the second data path of the first control/configure circuit is coupled to a first memory which stores the input data, and the fourth end of the second data path of the second control/configure circuit is coupled to the third end of the second data path of the third control/configure circuit. ### Claim 14 (depends on 13) The integrated circuit of claim 13 wherein: the plurality of data paths of each control/configure circuit further includes a third data path to output data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits at an end of an execution sequence, the third end of the third data path of the first control/configure circuit is configured to connect to the third end of the third data path of the second control/configure circuit, the fourth end of the third data path of the first control/configure circuit is coupled to a second memory which stores the output data, and the fourth end of the third data path of the second control/configure circuit is coupled to the third end of the second data path of the third control/configure circuit. ### Claim 15 (depends on 14) The integrated circuit of claim 14 further including: configurable processing circuitry, coupled to the fourth end of the third data path of the third control/configure circuit to: (i) receive the output data from each multiplier- accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits and (ii) process the output data wherein the processed output data are stored in the second memory. ### Claim 16 (depends on 15) The integrated circuit of claim 15 wherein: the configurable processing circuitry includes a plurality of configurable data path and one or more circuits connected therein, wherein the one or more circuits process the output data via addition/subtraction with a register value, multiplication by a register value, conversion from integer data format to floating point data format, conversion from floating point data format to integer data format, adjustment in format precision, and/or monadic function(s) including: inverse, square root, inverse square root, hyperbolic tangent and/or sigmoid. ### Claim 17 An integrated circuit comprising: a plurality of multiplier-accumulator circuits organized into a plurality of groups, wherein each group of multiplier-accumulator circuits includes a plurality of multiplier-accumulator circuits that is connected in series to perform a plurality of multiply and accumulate operations, wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of each group includes: a multiplier to multiply data by a multiplier weight data and generate a product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add input data and the product data of the associated multiplier to generate sum data; a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with one of the groups of multiplier-accumulator circuits, wherein each control/configure circuit includes: a plurality of data paths wherein each data path includes: a first end that directly connects to an input of a first multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of the associated group of multiplier-accumulator circuits, a second end that directly connects to an output of a last multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of the associated group of multiplier-accumulator circuits, wherein the first end of the data path couples to the second end of the data path through the plurality of serially connected multiplier-accumulator circuits of the associated group of the plurality of multiplier-accumulator circuits, a third end that is configurable to connect to an end of a corresponding data path of a different one of the plurality of control/configure circuits, and a fourth end; wherein the plurality of data paths of each control/configure circuit includes: a first data path to output data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits. ### Claim 18 (depends on 17) The integrated circuit of claim 17 wherein: the plurality of control/configure circuits includes a first control/configure circuit, a second control/configure circuit and a third control/configure circuit, the third end of the first data path of the first control/configure circuit is configured to connect to the third end of the first data path of the second control/configure circuit, the fourth end of the first data path of the first control/configure circuit is coupled to a memory which stores the output data, and the fourth end of the first data path of the second control/configure circuit is coupled to the third end of the second data path of the third control/configure circuit. ### Claim 19 (depends on 18) The integrated circuit of claim 18 wherein: the fourth end of the first data path of the third control/configure circuit is coupled to the memory which stores the output data at the end of the execution sequence. ### Claim 20 (depends on 18) The integrated circuit of claim 18 further including: configurable processing circuitry, coupled between the fourth end of the first data path of the third control/configure circuit and the memory, wherein the configurable processing circuitry is programmable to: (i) receive the output data from each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits and (ii) post-process the output data and stores the post-processed output data in the memory. ### Claim 21 (depends on 20) The integrated circuit of claim 20 wherein: the first data path receives data from memory, at the start of an execution sequence, to input into each multiplier-accumulator circuit of the plurality of serially connected multiplier-accumulator circuits of each group of the plurality of multiplier-accumulator circuits, and the fourth end of the first data path of the first control/configure circuit is coupled to the memory to receive the data from the memory at the start of an execution sequence. ### Claim 22 (depends on 18) The integrated circuit of claim 18 wherein: the fourth end of the first data path of the third control/configure circuit is coupled to the memory, and the integrated circuit further includes: configurable processing circuitry, coupled between the fourth end of the first data path of the third control/configure circuit and the memory, wherein the configurable processing circuitry includes at least one configurable data path and one or more circuits connected therein. ### Claim 23 (depends on 22) The integrated circuit of claim 22 wherein: the at least one configurable data path includes at least one multiplexer, and the one or more circuits include one or more circuits to process the output data via addition/subtraction with a register value, multiplication by a register value, conversion from integer data format to floating point data format, conversion from floating point data format to integer data format, adjustment in format precision, and/or monadic function(s) including: inverse, square root, inverse square root, hyperbolic tangent and/or sigmoid.