Interrupt request processing device

An interrupt request processing device comprising:

• one or more peripheral devices;
• one or more processor interfaces including a network interface;
• and
• one or more processors,
• wherein, when an interrupt request (IRQ) is generated, the peripheral device generates a packet including a peripheral device identification (ID) and a task ID and transmits the packet to the processor interface via an on-chip network,
• the processor interface receives and decodes the packet to transmit the IRQ signal to the processor and receives an interrupt vector generated from the processor to transmit an instruction and data corresponding to an activated interrupt request from an interrupt controller (IC) memory inside a processor interface to the processor,
• the processor outputs the interrupt vector in response to the IRQ signal and executes a corresponding interrupt service routine (ISR),
• the processor receives initial instructions and data from the processor interface via internal communication thereof and the peripheral device and the processor interface perform data communication via the on-chip network, and
• the processor interface includes an output interface which intercepts the interrupt vector generated by the processor in response to the IRQ signal, and an input interface which receives the interrupt vector from an output interface and then transmits an initial instruction corresponding to a currently activated interrupt signal to the processor using the peripheral device ID and the task ID of the packet stored inside the processor interface.