# US 11,442,878 B2 · Memory sequencer system and a method of memory sequencing using thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,878 B2 - Document ID: US11442878B2 - Status: Granted - Kind: B2 - Application number: 17/169,427 - Filed: 2021-02-06 - Published: 2022-05-26 - Granted: 2022-09-13 - Earliest claimed: 2020-11-20 - Assignees: Skyechip Sdn Bhd - Applicants: Skyechip Sdn Bhd - Inventors: Chee Hak Teh; Soon Chieh Lim - Web page: https://patentgrep.com/patent/US11442878B2 ## CPC - G06F 13/1668: {Details of memory controller} - G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)} - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A memory sequencer system for external memory protocols including a control center and a microcontroller; a control center network-on-chip having nodes connected point-to-point to synchronize and co-ordinate communication; whereby a command and address sequencer to generate command, control and address commands for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface; wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; wherein said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer to provide firmware controllability. ## Claims ### Claim 1 A memory sequencer system for external memory protocols, the memory sequencer system comprising: a control center including a microcontroller; a control center network-on-chip including nodes interconnected to synchronize and co-ordinate communications; a command and address sequencer to generate commands and addresses, and control the commands based on the respective addresses for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface, wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer; wherein said command and address sequencer includes a command sequence table to interpret each entry by cycling through said table to orchestrate command, address or data sequence generation; and wherein said address sequencer includes a set of adders or comparators to trigger incrementing of a different adder or comparator set within the same set based on a trigger value. ### Claim 2 (depends on 1) The memory sequencer system as claimed in claim 1, wherein said memory sequencer system is inserted in between a DDR PHY Interface of a memory controller and a physical layer transmit or receive path for the memory interface command and data. ### Claim 3 (depends on 1) The memory sequencer system as claimed in claim 1, wherein the command and address sequencer includes a command sequencer and an address sequencer. ### Claim 4 (depends on 3) The memory sequencer system as claimed in claim 3, wherein the command and address sequencer includes a command encoder and a command decoder. ### Claim 5 (depends on 1) The memory sequencer system as claimed in claim 1, wherein the data sequencer further includes a read data storage having a read data buffer. ### Claim 6 (depends on 1) The memory sequencer system as claimed in claim 1, wherein the control center network-on-chip connected to AXI-lite to receive, convert and deliver read or write commands into a network within the memory sequencer system. ### Claim 7 (depends on 1) The memory sequencer system as claimed in claim 1, wherein the control center network-on-chip includes a master node and a plurality of slave nodes organized in a tree topology, each node comprising a set of registers that is memory mapped to AXI memory space. ### Claim 8 (depends on 7) The memory sequencer system as claimed in claim 7, wherein the master node has multiple downstream ports, each slave node has one upstream port and multiple downstream ports. ### Claim 9 A method of memory sequencing for external memory protocols, the method comprising: generating command, address and data sequence for each entry; selecting one or more address sequencers for generating address; comparing a trigger value to trigger incrementing of adder or comparator at the address sequencers; chaining the adder or comparator to construct address sequences; encoding and decoding the command and address to trigger data path; implementing data latency with a shift register according to a number of clock cycles; transmitting the data including write data and read data to a data sequencer; converting AXI-lite read or write commands into control center network-on-chip read or write commands; transferring said control center network-on-chip read or write commands to targeted slave nodes of said control center network-on-chip based on the address and identification of said slave nodes; enumerating the slave nodes to assign the identification to each slave node; and synchronizing control center network-on-chip timestamp and alarm registers. ### Claim 10 (depends on 9) The method as claimed in claim 9, wherein the command, address and data sequence are generated according to programming values of a command sequence table. ### Claim 11 (depends on 10) The method as claimed in claim 10, wherein the programming values determines amount of delay for the command, address and data sequence. ### Claim 12 (depends on 9) The method as claimed in claim 9, wherein encoding a write command triggers write transmit data path and encoding a read command triggers read receive data path to capture and upload the data from the memory device. ### Claim 13 (depends on 9) The method as claimed in claim 9, wherein decoding a read command triggers write transmit data path and decoding a write command triggers read receive data path to capture and unload the data from the memory host. ### Claim 14 (depends on 9) The method as claimed in claim 9, wherein the step of transmitting the write data further comprising cycling through a write data sequence table to generate a write data transmitting pattern. ### Claim 15 (depends on 9) The method as claimed in claim 9, wherein the step of transmitting the read data further comprising cycling through a read data sequence table to generate a read data transmitting pattern. ### Claim 16 (depends on 9) The method as claimed in claim 9, wherein the step of transmitting the data to the data sequencer further comprising capturing read data in a read data buffer for debug and checking operations, signature generation, or bit comparison. ### Claim 17 (depends on 9) The method as claimed in claim 9, wherein the commands are transferred in a packet include a write packet, a read packet, a completion packet and a message packet. ### Claim 18 (depends on 9) The method as claimed in claim 9, wherein the step of synchronizing control center network-on-chip timestamp further comprising: sending a read packet from control center network-on-chip master node o one slave node; reading the timestamp register of the slave node; recording the sending time of the read packet; sending a read response to the read packet when the slave node receives the read packet; recording the receiving time of read response by control center network-on-chip master node; sending a write packet with current timestamp and pipeline delay data to the timestamp register of the slave node; and repeating the preceding steps from sending a read packet to slave node until all slave nodes have the same timestamp as control center network-on-chip master node; wherein the pipeline delay is half of a round trip delay; and the round trip delay is the difference between the receiving time of the read response and the sending time of read packet. ### Claim 19 (depends on 9) The method as claimed in claim 9, wherein the step of synchronizing control center network-on-chip timestamp further comprising: programming the timestamp offset register of control center network-on-chip master node and slave node with the number of clock cycles; broadcasting a write packet from control center network-on-chip master node o all slave nodes with a packet's data payload; setting the timestamp register value of slave node with the received data; sending the written timestamp value to the downstream slave node; and repeating the preceding steps from setting the timestamp register value until all slaves have the same timestamp as control center network-on-chip master node; wherein the write packet travel from control center network-on-chip master node to the control center network-on-chip slave node according to the number of clock cycles; and the data payload containing the timestamp value of the control center network-on-chip master node. ### Claim 20 The method as claimed in 18, wherein the timestamp is used in alarm triggering to perform synchronized actions across all slave node. ### Claim 21 The method as claimed in 19, wherein the timestamp is used in alarm triggering to perform synchronized actions across all slave node.