# US 11,442,877 B2 · Data bus duty cycle distortion compensation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,877 B2 - Document ID: US11442877B2 - Status: Granted - Kind: B2 - Application number: 16/949,510 - Filed: 2020-10-30 - Published: 2022-05-05 - Granted: 2022-09-13 - Earliest claimed: 2020-10-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Guan Wang; Ali Feiz Zarrin Ghalam; Chin-Yu Chen; Jongin Kim - Web page: https://patentgrep.com/patent/US11442877B2 ## CPC - G06F 13/1668: {Details of memory controller} - G11C 16/32: Timing circuits - G11C 29/021: {in voltage or current generators} - G11C 29/023: {in clock generator or timing circuitry} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/12005: {comprising voltage or current generators} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/16: using microprogrammed units, e.g. state machines - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H03K 5/1565: {the output pulses having a constant duty cycle} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value. ## Claims ### Claim 1 An electrical circuit device comprising: a signal bus comprising a plurality of parallel signal paths; and a calibration circuit, operatively coupled with the signal bus, the calibration circuit comprising: a multiple inputs integrator circuit coupled to the plurality of parallel signal paths, the multiple inputs integrator circuit to determine an average of a plurality of duty cycles for a plurality of signals transferred via the plurality of parallel signal paths; a comparator circuit coupled to the multiple inputs integrator circuit, the comparator circuit to compare the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result; a control system coupled to comparator circuit, the control system to adjust, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and a decoder circuit coupled to the control system, the decoder circuit to calibrate the plurality of duty cycles of the plurality of signals using the adjusted trim value. ### Claim 2 (depends on 1) The electrical circuit device of claim 1, wherein the multiple inputs integrator circuit comprises a plurality of passive low pass filters coupled to the plurality of parallel signal paths, the plurality of passive low pass filters to obtain a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals, and wherein an output of the multiple inputs integrator circuit comprises a DC level representation for the plurality of DC level representations. ### Claim 3 (depends on 2) The electrical circuit device of claim 2, wherein the comparator circuit is to convert the DC level representation into a representative digital signal representation, and wherein to compare the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to the reference value, the comparator circuit is to compare the DC level representation to the reference value. ### Claim 4 (depends on 1) The electrical circuit device of claim 1, wherein the reference value comprises one half of a voltage supply level. ### Claim 5 (depends on 1) The electrical circuit device of claim 1, wherein the decoder circuit is to convert the trim value into one or more biasing voltages and/or biasing currents and apply the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths to calibrate the plurality of duty cycles. ### Claim 6 (depends on 1) The electrical circuit device of claim 1, further comprising: a memory array, wherein the signal bus comprising the plurality of parallel signal paths is coupled to the memory array. ### Claim 7 (depends on 1) The electrical circuit device of claim 1, wherein the distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths. ### Claim 8 An electrical circuit device comprising: a signal bus comprising a plurality of parallel signal paths; and a calibration circuit, operatively coupled with the signal bus, to perform operations comprising: determining an average duty cycle of a plurality of duty cycles for a plurality of signals transferred via the plurality of parallel signal paths; comparing the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result; adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value. ### Claim 9 (depends on 8) The electrical circuit device of claim 8, wherein the calibration circuit is to perform further operations comprising: obtaining, using a plurality of passive low pass filters, a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals; determining a DC level representation for the plurality of DC level representations; and converting, using a comparator, the DC level representation into a representative digital signal representation. ### Claim 10 (depends on 9) The electrical circuit device of claim 9, wherein comparing the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to the reference value comprises comparing, using the comparator, the DC level representation to the reference value. ### Claim 11 (depends on 8) The electrical circuit device of claim 8, wherein the reference value comprises one half of a voltage supply level. ### Claim 12 (depends on 8) The electrical circuit device of claim 8, wherein the calibration circuit is to perform further operations comprising: converting the trim value into one or more biasing voltages and/or biasing currents; and calibrating the plurality of duty cycles by applying the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths. ### Claim 13 (depends on 8) The electrical circuit device of claim 8, further comprising: a memory array, wherein the signal bus comprising the plurality of parallel signal paths is coupled to the memory array. ### Claim 14 (depends on 8) The electrical circuit device of claim 8, wherein the distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths. ### Claim 15 A method comprising: determining an average duty cycle for a plurality of signals transferred via a plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles; comparing the average duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result; adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value. ### Claim 16 (depends on 15) The method of claim 15, further comprising: obtaining, using a plurality of passive low pass filters, a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals; determining a DC level representation for the plurality of DC level representations; and converting, using a comparator, the DC level representation into a representative digital signal representation. ### Claim 17 (depends on 16) The method of claim 16, wherein comparing the average duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to the reference value comprises comparing, using the comparator, the DC level representation to the reference value. ### Claim 18 (depends on 15) The method of claim 15, wherein the reference value comprises one half of a voltage supply level. ### Claim 19 (depends on 15) The method of claim 15, further comprising: converting the trim value into one or more biasing voltages and/or biasing currents; and calibrating the plurality of duty cycles by applying the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths. ### Claim 20 (depends on 15) The method of claim 15, wherein the distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths.