# US 11,442,872 B2 · Memory refresh operations using reduced power

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,442,872 B2
- Document ID: US11442872B2
- Status: Granted
- Kind: B2
- Application number: 16/545,949
- Filed: 2019-08-20
- Published: 2021-02-25
- Granted: 2022-09-13
- Earliest claimed: 2019-08-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Harish N. Venkata
- Web page: https://patentgrep.com/patent/US11442872B2

## CPC

- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- G06F 13/1673: {using buffers}
- G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/409: Read-write [R-W] circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

## Claims

### Claim 1

A device, comprising:
a plurality of memory banks comprising a first memory bank and a second memory bank, wherein each memory bank comprises a plurality of memory circuitries and is configured to store information; and
first sub-bank logic circuitry communicatively coupled to the first memory bank and the second memory bank via a plurality of multiplexers, wherein the first sub-bank logic circuitry is configured to couple to the first memory bank via the plurality of multiplexers and via a plurality of couplings that bypass the plurality of multiplexers, and wherein the first sub-bank logic circuitry transmits a control signal to refresh the second memory bank and the first memory bank when the plurality of multiplexers is operated to permit sharing of the control signal between the first memory bank and the second memory bank.

### Claim 2 (depends on 1)

The device of claim 1, wherein the control signal is shared with a first row of the first memory bank at the same time as when the control signal is shared with a first row of the second memory bank, wherein the first row of the first memory bank corresponds to a same row position as the first row of the second memory bank.

### Claim 3 (depends on 1)

The device of claim 1, wherein a respective multiplexer of the plurality of multiplexers is configured to couple to a memory channel via a buffer circuit.

### Claim 4 (depends on 3)

The device of claim 3, wherein the multiplexer is disposed external to the memory channel, and wherein the buffer circuit is disposed between the multiplexer and the memory channel.

### Claim 5 (depends on 1)

The device of claim 1, wherein the plurality of multiplexers is configured to directly couple to a plurality of memory channels.

### Claim 6 (depends on 5)

The device of claim 5, wherein the plurality of multiplexers is disposed internal to the plurality of memory channels, and wherein a buffer circuit couples the plurality of memory channels directly to the first sub-bank logic circuitry.

### Claim 7 (depends on 1)

The device of claim 1, wherein the control signal is transmitted from the first sub-bank logic circuitry in response to initiated refresh operations, and wherein the control signal is one of a plurality refresh control signals used to refresh individual rows of the first memory bank at least partially simultaneous to rows of the second memory bank.

### Claim 8 (depends on 7)

The device of claim 7, wherein the first memory bank is coupled to a second sub-bank logic circuitry, and wherein the second sub-bank logic circuitry is operated in a reduced-power operational mode during the refresh operations.

### Claim 9 (depends on 8)

The device of claim 8, wherein the reduced-power operational mode comprises removing power from the second sub-bank logic circuitry.

### Claim 10 (depends on 1)

The device of claim 1, comprising second sub-bank logic circuitry configured to be powered-off while the second memory bank is refreshed.

### Claim 11

A method, comprising:
performing, via a first bank logic circuitry, a memory operation;
receiving, via the first bank logic circuitry, an indication to initiate a refresh operation;
receiving, via the first bank logic circuitry, an indication to operate in a reduced-power operation;
transmitting, via the first bank logic circuitry, a refresh control signal to buffer circuitry coupled to a multiplexer to initiate a reduced-power refresh operation, wherein the multiplexer is coupled between the first bank logic circuitry, a second bank logic circuitry, and a memory bank, wherein the reduced-power refresh operation enables power supplied to the second bank logic circuitry to be reduced while a refresh of the memory bank occurs.

### Claim 12 (depends on 11)

The method of claim 11, comprising transmitting a plurality of refresh control signals comprising the refresh control signal, and wherein an amount of the plurality of refresh control signals is equal to half an amount of a plurality of memory banks comprising the memory bank.

### Claim 13 (depends on 11)

The method of claim 11, comprising removing the second bank logic circuitry from its power supply.

### Claim 14 (depends on 11)

The method of claim 11, comprising transmitting a plurality of operational control signals to a plurality of multiplexers to change a state of each of the plurality of multiplexers such that signals are able to be shared between the first bank logic circuitry and the memory bank without sharing signals from the second bank logic circuitry, wherein the plurality of multiplexers comprises the multiplexer.

### Claim 15

A system, comprising:
a memory controller; and
a memory module communicatively coupled to the memory controller, wherein the memory module comprises:
first bank logic circuitry coupled to a first memory bank;
second bank logic circuitry configured to be coupled to a second memory bank and powered-off while the second memory bank is refreshed; and
a switching circuit configured to couple the first bank logic circuitry to the second memory bank instead of the second bank logic circuitry during memory refresh operations in response to a control signal from the memory controller.

### Claim 16 (depends on 15)

The system of claim 15, wherein the memory module comprises a memory channel region used to transmit one or more control signals between the first memory bank and the first bank logic circuitry.

### Claim 17 (depends on 16)

The system of claim 16, wherein the switching circuit is disposed within the memory channel region.

### Claim 18 (depends on 16)

The system of claim 16, wherein the switching circuit is disposed external to the memory channel region and coupled between a buffer and the first bank logic circuitry.

### Claim 19 (depends on 15)

The system of claim 15, wherein the memory controller is configured to power-off the second bank logic circuitry at least in part by:
transmitting a first indication to cause the first bank logic circuitry to initiate a refresh operation associated with the memory module;
transmitting a second indication to cause the second bank logic circuitry to be removed from power; and
transmitting a refresh control signal to the first bank logic circuitry, wherein the first bank logic circuitry transmits the refresh control signal onto the memory.

### Claim 20 (depends on 15)

The system of claim 15, wherein the switching circuit is coupled to a first communicative coupling that routes between the first bank logic circuitry and the first memory bank and a second communicative coupling that routes between the second bank logic circuitry and the second memory bank.