# US 11,442,870 B2 · Information processing apparatus having an integrated circuit chip with first and second communication units having address translation function > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,870 B2 - Document ID: US11442870B2 - Status: Granted - Kind: B2 - Application number: 17/190,750 - Filed: 2021-03-03 - Published: 2021-09-16 - Granted: 2022-09-13 - Earliest claimed: 2020-03-16 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Takeshi Kuga - Web page: https://patentgrep.com/patent/US11442870B2 ## CPC - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 13/4295: {using an embedded synchronisation} - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 12/1441: {for a range} - G06F 13/1668: {Details of memory controller} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 2212/1016: Performance improvement - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Each of a plurality of IC chips, which are connected in series, is configured such that each IC chip access an entire memory space of each of other IC chips. ## Claims ### Claim 1 An information processing apparatus that includes a plurality of integrated circuit (IC) chips which are connected in series, wherein at least one target IC chip of the plurality of IC chips comprises: a memory space accessible at a first address width; a CPU configured to perform processing in a range which is in the memory space and is accessible at a second address width smaller than the first address width; a first communication unit, having an address translation function, for performing communication with one IC chip of the plurality of IC chips which are connected in series; and a second communication unit, having the address translation function, for performing communication with an IC chip in an opposite direction to the one IC chip, wherein a first area for accessing the one IC chip via the first communication unit and a second area for accessing the IC chip in the opposite direction via the second communication unit are included in the memory space, the CPU included in the target IC chip accesses one of the first communication unit and the second communication unit by using the range which is in the memory space and is accessible at the second address width, in a case in which the CPU accesses the first communication unit, a first address value used to access the first communication unit by the address translation function of the first communication unit is translated into a second address value which corresponds to the first area of the memory space of the first address width, an access to the one IC chip specified by the second address value is executed, in a case in which the CPU accesses the second communication unit, a third address value used to access the second communication unit by the address translation function of the second communication unit is translated into a fourth address value which corresponds to the second area of the memory space of the first address width, an access to an IC chip in the opposite direction specified by the fourth address value is executed, in a case in which one communication unit of the first communication unit and the second communication unit included in the target IC chip accepts an access by an address value specified from another IC chip of the plurality of IC chips and the specified address value is included in a predetermined range, the access from the other IC chip is processed as an access to the target IC chip, and in a case in which the one communication unit of the first communication unit and the second communication unit included in the target IC chip accepts the access by the address value specified from the other chip and the specified address value is not included in the predetermined range, the access from the other IC chip accepted by the first communication unit is transferred to the second communication unit, and the access from the other IC chip accepted by the second communication unit is transferred to the first communication unit. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein an address value used for accessing the memory space of the target IC chip is formed by a predetermined first number of upper bits for specifying the target IC chip and a predetermined second number of lower bits for specifying a range that can be accessed by the second address width of the target IC chip. ### Claim 3 (depends on 2) The apparatus according to claim 2, wherein in the address value used for accessing the memory space of the target IC chip, address translation is performed by deleting the predetermined first number of upper bits and extracting the predetermined second number of lower bits for specifying the range that can be accessed by the second address width of the target IC chip. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein each of the plurality of IC chips further comprises a ROM configured to store a program, and in a case in which a power supply of the information processing apparatus is set to ON, each of the plurality of the IC chips will read out the program from the ROM and perform initialization. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein one IC chip of the plurality of IC chips comprises a ROM configured to store a program, and in a case in which a power supply of the information processing apparatus is set to ON, the one IC chip reads out the program from the ROM and performs initialization, the program is transferred to another IC chip after the initialization, and the other IC chip performs initialization by the transferred program. ### Claim 6 (depends on 1) The apparatus according to claim 1, wherein each of the plurality of IC chips further comprises a direct memory access controller (DMAC). ### Claim 7 (depends on 6) The apparatus according to claim 6, wherein the plurality of IC chips are connected by PCI-Express, and a data transfer between the plurality of IC chips includes at least one of a transfer performed by the PCI-Express via the DMAC and a transfer performed by the PCI-Express via the CPU. ### Claim 8 (depends on 1) The apparatus according to claim 1, wherein the information processing apparatus is an inkjet printing apparatus, one IC chip of the plurality of IC chips is assigned to control the entire inkjet printing apparatus and to communicate with a host to which the inkjet printing apparatus is connected, and the remaining IC chip of the plurality of IC chips is assigned for image processing of data to perform printing by controlling a printhead. ### Claim 9 (depends on 8) The apparatus according to claim 8, wherein the remaining IC chip is assigned for image processing of color component data corresponding to a color of ink to be discharged by the printhead. ### Claim 10 An information processing apparatus that includes a plurality of integrated circuit (IC) chips which are connected in series, wherein at least one target IC chip of the plurality of IC chips comprises: a memory space accessible accessed at a first address width; a CPU configured to perform processing in a range which is in the memory space and is accessible at a second address width smaller than the first address width; a first communication unit, having an address translation function, for performing communication with one IC chip of the plurality of IC chips which are connected in series; and a second communication unit, having the address translation function, for performing communication with an IC chip in an opposite direction to the one IC chip, wherein a first area for accessing the one IC chip via the first communication unit and a second area for accessing the IC chip in the opposite direction via the second communication unit are included in the memory space, the CPU included in the target IC chip accesses one of the first communication unit and the second communication unit by using the range which is in the memory space and is accessible at the second address width, in a case in which the CPU accesses the first communication unit, a first address value used to access the first communication unit by the address translation function of the first communication unit is translated into a second address value which corresponds to the first area of the memory space of the first address width, an access to the one IC chip specified by the second address value is executed in a case in which the CPU accesses the second communication unit, a third address value used to access the second communication unit by the address translation function of the second communication unit is translated into a fourth address value which corresponds to the second area of the memory space of the first address width, and an access to an IC chip in the opposite direction specified by the fourth address value is executed. ### Claim 11 An information processing apparatus that includes a plurality of integrated circuit (IC) chips which are connected in series, wherein at least one target IC chip of the plurality of IC chips comprises: a memory space accessible at a first address width; a CPU configured to perform processing in a range which is in the memory space and is accessible at a second address width smaller than the first address width; a first communication unit, having an address translation function, for performing communication with one IC chip of the plurality of IC chips which are connected in series; and a second communication unit, having the address translation function, for performing communication with an IC chip in an opposite direction to the one IC chip, wherein a first area for accessing the one IC chip via the first communication unit and a second area for accessing an IC chip in the opposite direction via the second communication unit are included in the memory space, the CPU included in the target IC chip accesses one of the first communication unit and the second communication unit by using the range which is in the memory space and is accessible at the second address width, in a case in which the first communication unit included in the target IC chip accepts an access from the one IC chip based on a specified address value in the first area and the specified address value is included in a predetermined range, the access from the one IC chip is processed as an access to the target IC chip, in a case in which the first communication unit included in the target IC chip accepts the access from the one IC chip based on the specified address value in the first area and the specified address value is not included in the predetermined range, the access accepted by the first communication unit is transferred to the second communication unit, in a case in which the second communication unit included in the target IC chip accepts an access from the IC chip in the opposite direction based on a specified address value in the second area and the specified address value is included in a predetermined range, the access from the IC chip in the opposite direction is processed as an access to the target IC chip, and in a case in which the second communication unit included in the target IC chip accepts the access from the IC chip in the opposite direction based on the specified address value in the second area and the specified address value is not included in the predetermined range, the access accepted by the second communication unit is transferred to the first communication unit.