# US 11,442,868 B2 · Aggressive write flush scheme for a victim cache

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- Number: US 11,442,868 B2
- Document ID: US11442868B2
- Status: Granted
- Kind: B2
- Application number: 16/882,374
- Filed: 2020-05-22
- Published: 2020-11-26
- Granted: 2022-09-13
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen Bhoria; Timothy David Anderson; Pete Hippleheuser
- Web page: https://patentgrep.com/patent/US11442868B2

## CPC

- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/12: Replacement control
- G06F 12/121: using replacement algorithms
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/127: using additional replacement algorithms
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1642: {with request queuing}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 15/8069: {using a cache}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/106: {Data output latches}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/72: {with optimized replacement algorithms}
- G11C 29/76: {using address translation or modifications}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1041: Resource optimization
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/301: In special purpose processing node, e.g. vector processor
- G06F 2212/454: Vector or matrix data
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G11C 29/4401: {for self repair}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

## Claims

### Claim 1

A caching system comprising:
a first sub-cache; and
a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes:
a set of cache lines;
line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data; and
an eviction controller configured to:
determine that a first cache line of the second sub-cache storing write-miss data is full; and
evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.

### Claim 2 (depends on 1)

The caching system of claim 1, wherein the eviction controller is further configured to:
determine that a second cache line of the second sub-cache storing write-miss data is half full; and
evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

### Claim 3 (depends on 2)

The caching system of claim 2, wherein the eviction controller is configured to determine that no cache line of the second sub-cache storing write-miss data is fully written before evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

### Claim 4 (depends on 2)

The caching system of claim 2,
wherein the second sub-cache further comprises a byte enable memory configured to store byte enable logic associated with the stored write-miss data,
wherein the byte enable memory includes a first bit,
wherein a value of the first bit indicates whether the first cache line is full, and
wherein the eviction controller is configured to determine that the first cache line is full by at least reading the value of the first bit.

### Claim 5 (depends on 4)

The caching system of claim 4,
wherein the byte enable memory includes a second bit, and
wherein a value of the second bit indicates whether the second cache line is half full, and
wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.

### Claim 6 (depends on 5)

The caching system of claim 5, wherein the first and second bits are determined based on the byte enable logic associated with the stored write-miss data.

### Claim 7 (depends on 6)

The caching system of claim 6, wherein the first and second bits are determined based on the byte enable logic each time write-miss data is stored in the second sub-cache.

### Claim 8

A method for caching data, comprising:
receiving, by a caching system, a write memory request for a memory address;
determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache;
determining, by a second sub-cache of the caching system, that the memory address is not cached in the second sub-cache;
responsive to determining that the memory address is not cached in the second sub-cache, storing data associated with the write memory request in a first cache line of the second sub-cache;
responsive to determining that the memory address is not cached in the second sub-cache, storing, in a line type bit of the second sub-cache, an indication that the stored data corresponds to a write-miss;
determining that the first cache line is full; and
evicting write-miss data stored in the first cache line in response to determining that the first cache line is full.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
determining that a second cache line of the second sub-cache storing write-miss data is half full; and
evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

### Claim 10 (depends on 9)

The method of claim 9, further comprising determining that no cache line of the second sub-cache storing write-miss data is fully written before evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

### Claim 11 (depends on 9)

The method of claim 9, further comprising storing a first bit in a byte enable memory of the second sub-cache,
wherein a value of the first bit indicates whether the first cache line is full, and
wherein determining that the first cache line is full by at least reading the value of the first bit.

### Claim 12 (depends on 11)

The method of claim 11, further comprising storing a second bit in the byte enable memory of the second sub-cache,
wherein a value of the second bit indicates whether the second cache line is half full, and
wherein determining that the second cache line is half full by at least reading the value of the second bit.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first and second bits are determined based on the byte enable logic associated with the stored write-miss data.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first and second bits are determined based on the byte enable logic each time write-miss data is stored in the second sub-cache.

### Claim 15

A device comprising:
a processor;
a first sub-cache; and
a second sub-cache in parallel with the first sub-cache; wherein the second sub-cache includes:
a set of cache lines;
line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and
an eviction controller configured to:
determine that a first cache line of the second sub-cache storing write-miss data is full; and
evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.

### Claim 16 (depends on 15)

The device of claim 15, wherein the eviction controller is further configured to:
determine that a second cache line of the second sub-cache storing write-miss data is half full; and
evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

### Claim 17 (depends on 16)

The device of claim 16, wherein the eviction controller is configured to determine that no cache line of the second sub-cache storing write-miss data is fully written before evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

### Claim 18 (depends on 16)

The device of claim 16,
wherein the second sub-cache further comprises a byte enable memory configured to store byte enable logic associated with the stored write-miss data,
wherein the byte enable memory includes a first bit,
wherein a value of the first bit indicates whether the first cache line is full, and
wherein the eviction controller is configured to determine that the first cache line is full by at least reading the value of the first bit.

### Claim 19 (depends on 18)

The device of claim 18,
wherein the byte enable memory includes a second bit,
wherein a value of the second bit indicates whether the second cache line is half full, and
wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.

### Claim 20 (depends on 19)

The device of claim 19, wherein the first and second bits are determined based on the byte enable logic associated with the stored write-miss data.