# US 11,442,866 B2 · Computer memory module processing device with cache storage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,866 B2 - Document ID: US11442866B2 - Status: Granted - Kind: B2 - Application number: 16/783,924 - Filed: 2020-02-06 - Published: 2021-06-24 - Granted: 2022-09-13 - Earliest claimed: 2019-12-20 - Assignees: Meta Platforms, Inc. - Applicants: Meta Platforms, Inc. - Inventors: Liu Ke; Xuan Zhang; Udit Gupta; Carole-Jean Wu; Mark David Hempstead; Brandon Reagen; Hsien-Hsin Sean Lee - Web page: https://patentgrep.com/patent/US11442866B2 ## CPC - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 2212/452: Instruction code - G06F 2212/608: Details relating to cache mapping - G06N 20/00: Machine learning - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A device (e.g., an application-specific integrated circuit chip) includes a memory module processing unit and an interface. The memory module processing unit is configured to receive an instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result. The memory module processing unit is also configured to store the obtained values in a cache based on one or more criteria. The memory module processing unit is configured to be included on a computer memory module configured to be installed in a computer system. The interface is configured to communicate with the one or more memory components included on the computer memory module. ## Claims ### Claim 1 A device, comprising: a memory module processing unit configured to: receive an instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result; and store the obtained values in a cache based on one or more criteria; wherein: the memory module processing unit is configured to be included on a computer memory module configured to be installed in a computer system; and the memory module processing unit includes a primary processing component and a plurality of secondary processing components communicatively connected to the primary processing component, wherein: the primary processing component is configured to receive the instruction and transmit the instruction to the plurality of secondary processing components; the primary processing component includes a hardware component configured to queue multiple instructions and distribute the queued multiple instructions to the plurality of secondary processing components; and at least one secondary processing component of the plurality of secondary processing components includes: an instruction buffer configured to receive the instruction from the primary processing component; and instruction decoding circuitry configured to determine a value of a field within the instruction, wherein the value of the field indicates whether the values stored in the one or more memory components are also located in the cache; and an interface configured to communicate with the one or more memory components included on the computer memory module. ### Claim 2 (depends on 1) The device of claim 1, wherein the instruction is an embedding operation. ### Claim 3 (depends on 2) The device of claim 2, wherein the embedding operation includes a summation computation. ### Claim 4 (depends on 1) The device of claim 1, wherein at least one of the one or more memory components is a dynamic random-access memory device. ### Claim 5 (depends on 1) The device of claim 1, wherein the memory module processing unit is configured to process the obtained values including by being configured to sum the obtained values. ### Claim 6 (depends on 1) The device of claim 1, wherein the memory module processing unit is configured to process the obtained values including by being configured to apply weights to the obtained values. ### Claim 7 (depends on 1) The device of claim 1, wherein the memory module processing unit is configured to process the obtained values including by being configured to quantize the obtained values. ### Claim 8 (depends on 1) The device of claim 1, wherein the one or more criteria include a determination that the obtained values are accessed a specified number of times over a specified time period. ### Claim 9 (depends on 1) The device of claim 1, wherein the computer memory module is a dual-inline memory module. ### Claim 10 (depends on 1) The device of claim 1, wherein the computer system includes a memory controller that interfaces with the memory module processing unit. ### Claim 11 (depends on 1) The device of claim 1, wherein the interface is a dynamic random-access memory device interface that supports a protocol for communicating double data rate compatible command, address, and data signals. ### Claim 12 (depends on 1) The device of claim 1, further comprising the one or more memory components. ### Claim 13 (depends on 1) The device of claim 1, further comprising the cache. ### Claim 14 (depends on 13) The device of claim 13, wherein the cache is communicatively connected to an instruction decoder. ### Claim 15 (depends on 1) The device of claim 1, wherein the instruction is utilized in a personalized recommendation system operation. ### Claim 16 (depends on 1) The device of claim 1, wherein the one or more memory components are configured as a plurality of memory ranks that supports parallel access. ### Claim 17 (depends on 1) The device of claim 1, wherein the interface is configured to communicate with the one or more memory components including by being configured to transmit double data rate commands in a compressed format. ### Claim 18 (depends on 1) The device of claim 1, wherein the instruction is in a format that includes one or more of the following fields: an op code field, a double data rate command field, a data address field, and a data size field. ### Claim 19 A method, comprising: using a memory module processing unit that is configured to be included on a computer memory module configured to be installed in a computer system to receive an instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result; using the memory module processing unit to store the obtained values in a cache based on one or more criteria; and using an interface to communicate with the one or more memory components included on the computer memory module; wherein the memory module processing unit includes a primary processing component and a plurality of secondary processing components communicatively connected to the primary processing component, wherein: the primary processing component is configured to receive the instruction and transmit the instruction to the plurality of secondary processing components; the primary processing component includes a hardware component configured to queue multiple instructions and distribute the queued multiple instructions to the plurality of secondary processing components; and at least one secondary processing component of the plurality of secondary processing components includes: an instruction buffer configured to receive the instruction from the primary processing component; and instruction decoding circuitry configured to determine a value of a field within the instruction, wherein the value of the field indicates whether the values stored in the one or more memory components are also located in the cache. ### Claim 20 A device, comprising: a first memory module processing unit configured to: receive a first instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result; and store the obtained values in a cache based on one or more criteria; wherein: the first memory module processing unit is configured to be included on a computer memory module configured to be installed in a computer system; and the first memory module processing unit includes a primary processing component and a plurality of secondary processing components communicatively connected to the primary processing component, wherein: the primary processing component is configured to receive the first instruction and transmit the first instruction to the plurality of secondary processing components; the primary processing component includes a hardware component configured to queue multiple instructions and distribute the queued multiple instructions to the plurality of secondary processing components; and at least one secondary processing component of the plurality of secondary processing components includes: an instruction buffer configured to receive the instruction from the primary processing component; and instruction decoding circuitry configured to determine a value of a field within the instruction, wherein the value of the field indicates whether the values stored in the one or more memory components are also located in the cache; an interface configured to communicate with the one or more memory components included on the computer memory module; and a second memory module processing unit configured to receive a second instruction, wherein the second instruction has a format that is different from that of the first instruction.