# US 11,442,861 B2 · Semiconductor device and cache control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,861 B2 - Document ID: US11442861B2 - Status: Granted - Kind: B2 - Application number: 17/337,048 - Filed: 2021-06-02 - Published: 2022-01-27 - Granted: 2022-09-13 - Earliest claimed: 2020-07-22 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Yasunobu Akizuki - Web page: https://patentgrep.com/patent/US11442861B2 ## CPC - G06F 12/084: with a shared cache - G06F 12/0842: for multiprocessing or multitasking - G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)} - G06F 11/3471: {Address tracing} - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 12/0886: Variable-length word access - G06F 2201/81: Threshold - G06F 2201/88: Monitoring involving counting - G06F 2201/885: Monitoring specific for caches - G06F 2212/502: using adaptive policy - G06F 2212/601: Reconfiguration of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor device includes a plurality of cores, each including an instruction execution circuit and a first cache, and a second cache shared by the plurality of cores. In each of the cores, a number of completed instructions for each type of the instructions executed by the instruction execution circuit are counted, and an execution frequency for each type of instructions are calculated. Based on the execution frequencies, a cache line size preferable for use in the first cache in the core is selected. Based on the selected preferable cache line sizes for the cores, a cache line size used in the first caches and the second cache is determined. ## Claims ### Claim 1 A semiconductor device comprising: a plurality of cores each including an instruction execution circuit that executes an instruction and a first cache that holds at least one of an instruction and data used in the instruction execution circuit; a second cache shared by the plurality of cores; and a cache control circuit that controls switching of a cache line size used in the first cache and the second cache, wherein each of the plurality of cores further including an instruction collection circuit that collects, at time intervals during a collection period, a number of completed instructions for each type of the instructions that are executed by the instruction execution circuit, and calculates an execution frequency for each type of the instructions at an end of the collection period, and a first selection circuit that selects a cache line size for use in the first cache based on the execution frequency calculated by the instruction collection circuit during the collection period, and the cache control circuit determines a cache line size used in the first cache and the second cache based on cache line sizes selected by the first selection circuit of the plurality of cores. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein when an execution frequency of instructions of a first type among instruction types exceeds a first threshold, the first selection circuit selects the cache line size for use in the first cache depending on whether an execution frequency of instructions of a second type among the instruction types exceeds a second threshold. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein each of the plurality of cores executes instructions by a single thread or multiple threads, and when the execution frequency of the instructions of the first type is equal to or less than the first threshold, the first selection circuit selects the cache line size for use in the first cache depending on whether an instruction is executed by the single thread or the multiple threads. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein when the number of instructions executed by the instruction execution circuit during the collection period is equal to or less than a third threshold, the first selection circuit does not select a cache line size, and the cache line size used in the first cache and the second cache previously selected is maintained. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the cache control circuit includes a second selection circuit that selects, at every completion of the collection period, a cache line size most selected by the first selection circuits of the plurality of cores as a cache line size for use in the first cache and the second cache, a history holding circuit that holds a cache line size selected by the second selection circuit at every completion of a predetermined number of past collection periods, and a cache line size determination circuit that determines, when a cache line size selected by the second selection circuit at completion of a latest collection period matches all of the plurality of cache line sizes held in the history holding circuit, the cache line size selected by the second selection circuit as the cache line size used in the first cache and the second cache. ### Claim 6 (depends on 5) The semiconductor device according claim 5, wherein the cache control circuit includes a cache line size holding circuit including, corresponding to each of the plurality of cores, an entry including a valid flag to be set based on notification of selection or non-selection of a cache line size from the core, a valid core flag that identifies selection or non-selection of a cache line size, and a storage area that stores a cache line size selected by the core, and when the valid flag is set in all the entries of the cache line size holding circuit, the second selection circuit selects a cache line size based on cache line sizes stored in the storage areas of the entries in each of which the valid core flag indicates selection of the cache line size. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the instruction collection circuit includes an instruction count circuit that counts a number of instructions for which execution is completed by the instruction execution circuit, a plurality of type count circuits each of which counts a number of instructions for which executions are completed by the instruction execution circuit for each type, and a frequency calculation circuit that calculates an execution frequency, for each type of the instructions, based on the number of instructions counted by the instruction count circuit and the number of instructions counted by each of the plurality of type count circuit for each type. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein each type of the instructions includes one of single instruction/multiple data (SIMD) instruction and a discrete access instruction. ### Claim 9 A cache control method for switching a cache line size in a semiconductor device comprising: a plurality of cores each including an instruction execution circuit that executes an instruction and a first cache that holds at least one of an instruction and data used in the instruction execution circuit; and a second cache shared by the plurality of cores; the method including: collecting, for each of the plurality of cores, at time intervals during a collection period, a number of completed instructions for each type of the instructions that are executed by the instruction execution circuit; calculating, for each of the plurality of cores, an execution frequency for each type of the instructions at an end of the collection period, selecting, for each of the plurality of cores, a cache line size for use in the first cache based on the execution frequency calculated, and determining a cache line size used in the first cache and the second cache based on cache line sizes selected for the plurality of cores. ### Claim 10 (depends on 9) The cache control method according to claim 9, wherein the selecting selects the cache line size for use in the first cache depending on whether an execution frequency of instructions of a second type among the instruction types exceeds a second threshold when an execution frequency of instructions of a first type among instruction types exceeds a first threshold. ### Claim 11 (depends on 10) The cache control method e according to claim 10, wherein each of the plurality of cores executes instructions by a single thread or multiple threads, and when the execution frequency of the instructions of the first type is equal to or less than the first threshold, the selecting selects the cache line size for use in the first cache depending on whether an instruction is executed by the single thread or the multiple threads. ### Claim 12 (depends on 9) The cache control method according to claim 9, wherein when the number of instructions executed during the collection period is equal to or less than a third threshold, the cache line size is not selected, and the cache line size used in the first cache and the second cache previously selected is maintained. ### Claim 13 (depends on 9) The cache control method according to claim 9, further comprising: selecting, at every completion of the collection period, a cache line size most selected by first selection circuits of the plurality of cores as a cache line size for use in the first cache and the second cache, holding a cache line size selected by a second selection circuit at every completion of a predetermined number of past collection periods, and determining, when a cache line size selected by the second selection circuit at completion of a latest collection period matches all of the plurality of cache line sizes held in the history holding circuit, the cache line size selected by the second selection circuit as the cache line size used in the first cache and the second cache. ### Claim 14 (depends on 13) The cache control method according claim 13, wherein the holding holds a cache line size corresponding to each of the plurality of cores, an entry including a valid flag to be set based on notification of selection or non-selection of a cache line size from the core, a valid core flag that identifies selection or non-selection of a cache line size, and a storage area that stores a cache line size selected by the core, and when the valid flag is set in all the entries of a cache line size holding circuit, selecting a cache line size based on cache line sizes stored in the storage areas of the entries in each of which the valid core flag indicates selection of the cache line size. ### Claim 15 (depends on 9) The cache control method according to claim 9, further comprising: counting a number of instructions for which execution is completed by the instruction execution circuit, counting, with a plurality of type count circuits, a number of instructions for which executions are completed by the instruction execution circuit for each type, and calculating an execution frequency, for each type of the instructions, based on the number of instructions counted by the instruction count circuit and the number of instructions counted by each of the plurality of type count circuit for each type. ### Claim 16 (depends on 9) The cache control method according to claim 9, wherein each type of the instructions includes one of single instruction/multiple data (SIMD) instruction and a discrete access instruction.