# US 11,442,858 B1 · Bias control for a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,858 B1 - Document ID: US11442858B1 - Status: Granted - Kind: B1 - Application number: 17/198,084 - Filed: 2021-03-10 - Published: 2022-09-15 - Granted: 2022-09-13 - Earliest claimed: 2021-03-10 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Dean Walker; Bryan D. Hornung; Tony M. Brewer; David M. Patrick; Christopher A. Baronne - Web page: https://patentgrep.com/patent/US11442858B1 ## CPC - G06F 12/0815: Cache consistency protocols - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 2212/1041: Resource optimization - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value. ## Claims ### Claim 1 A system, comprising: a memory; and a controller coupled with the memory, wherein the controller is configured to: store a coherency state for a set of data stored in the memory relative to a cache of a host device; and access the memory according to a bias state for the set of data determined based at least in part on the stored coherency state for the set of data based at least in part on identifying a command to perform an access operation for the set of data stored in the memory, wherein the bias state is associated with control of access for the set of data by the controller. ### Claim 2 (depends on 1) The system of claim 1, wherein the controller is configured to access the memory independent of the host device based at least in part on the bias state. ### Claim 3 (depends on 2) The system of claim 2, further comprising: a cache associated with the memory, wherein the command comprises a read command, and wherein the controller is configured to: determine that the set of data is stored to the cache associated with the memory based at least in part on identifying the command; and accessing the set of data stored to the cache based at least in part on determining that the set of data is stored to the cache. ### Claim 4 (depends on 3) The system of claim 3, wherein the controller is configured to: determine that a second set of data is not stored to the cache based at least in part on identifying a command to perform an access operation for the second set of data; and access the memory according to a second bias state for the second set of data based at least in part on determining that the second set of data is not stored to the cache, wherein the second bias state is associated with control of access for the second set of data by the host device. ### Claim 5 (depends on 1) The system of claim 1, wherein the memory is configured to store a first value that is associated with a first coherency state for the set of data, a second value that is associated with a second coherency state for the set of data, or a third value that is associated with a third coherency state for the set of data. ### Claim 6 (depends on 5) The system of claim 5, wherein: the first value indicates that the set of data is not coherent; and the second value and the third value indicate that the set of data is coherent, wherein the controller is configured to process the command according to the bias state based at least in part on the memory storing the first value for the set of data. ### Claim 7 (depends on 1) The system of claim 1, wherein the set of data is associated with a first quantity of data, and wherein a cache line of the host device coupled with the memory is configured to store the first quantity of data. ### Claim 8 (depends on 1) The system of claim 1, wherein the bias state corresponds to a first bias state, and wherein a second bias state is associated with control of access for the set of data by the host device. ### Claim 9 A system, comprising: a memory; and a controller coupled with the memory, wherein the controller is configured to: store a coherency state for a set of data stored in the memory relative to a cache of a host device; and access the memory according to a bias state for the set of data determined based at least in part on the stored coherency state for the set of data based at least in part on identifying a command to perform an access operation for the set of data stored in the memory, wherein the bias state is associated with control of access for the set of data by the host device. ### Claim 10 (depends on 9) The system of claim 9, wherein the controller is configured to store the coherency state for the set of data independent from the command, wherein the controller is configured to: transmit, to the host device, an indication of the access operation to be performed on the set of data based at least in part on determining to process the command according to the bias state; and receive, from the host device, a second command for indicating direct access for the set of data for the access operation based at least in part on transmitting the indication of the access operation. ### Claim 11 (depends on 10) The system of claim 10, wherein the controller is configured to access the memory for the set of data based at least in part on receiving the second command from the host device. ### Claim 12 (depends on 9) The system of claim 9, wherein the memory is configured to store a first value that is associated with a first coherency state for the set of data, a second value that is associated with a second coherency state for the set of data, or a third value that is associated with a third coherency state for the set of data. ### Claim 13 (depends on 12) The system of claim 12, wherein: the first value indicates that an invalid version of the set of data is stored to the cache of the host device; the second value indicates that a shared version or an exclusive version of the set of data is stored to the cache of the host device; and the third value indicates that the shared version of the set of data is stored to the cache of the host device. ### Claim 14 (depends on 12) The system of claim 12, wherein the second value and the third value indicate that the set of data is coherent, and wherein the controller is configured to process the command according to the bias state based at least in part on the memory storing the second value or the third value for the set of data. ### Claim 15 (depends on 9) The system of claim 9, wherein the set of data is associated with a first quantity of data, and wherein a cache line of the host device coupled with the memory is configured to store the first quantity of data. ### Claim 16 (depends on 9) The system of claim 9, wherein a first bias state is associated with control of access for the set of data by the controller, and wherein the bias state corresponds to a second bias state. ### Claim 17 A method, comprising: storing a coherency state for a set of data stored in a memory relative to a cache of a host device; and accessing the memory according to a bias state for the set of data determined based at least in part on the stored coherency state for the set of data based at least in part on identifying a command to perform an access operation for the set of data stored in the memory, wherein the bias state is associated with control of access for the set of data by a controller associated with the memory. ### Claim 18 (depends on 17) The method of claim 17, further comprising: accessing the memory independent of the host device based at least in part on the bias state. ### Claim 19 (depends on 18) The method of claim 18, wherein the command comprises a read command, the method further comprising: determining that the set of data is stored to a cache associated with the memory; and accessing the set of data stored to the cache based at least in part on determining that the set of data is stored to the cache associated with the memory. ### Claim 20 (depends on 17) The method of claim 17, wherein the memory is configured to store a first value that is associated with a first coherency state for the set of data, a second value that is associated with a second coherency state for the set of data, or a third value that is associated with a third coherency state for the set of data. ### Claim 21 (depends on 20) The method of claim 20, wherein: the first value indicates that the set of data is not coherent; and the second value and the third value indicate that the set of data is coherent, wherein the controller is configured to process the command according to the bias state based at least in part on the memory storing the first value for the set of data. ### Claim 22 (depends on 17) The method of claim 17, wherein the set of data is associated with a first quantity of data, and wherein a cache line of the host device coupled with the memory is configured to store the first quantity of data. ### Claim 23 (depends on 17) The method of claim 17, wherein the bias state corresponds to a first bias state, and wherein a second bias state is associated with control of access for the set of data by the host device. ### Claim 24 A method, comprising: storing a coherency state for a set of data stored in a memory relative to a cache of a host device; and accessing the memory according to a bias state for the set of data determined based at least in part on the stored coherency state for the set of data based at least in part on identifying a command to perform an access operation for the set of data stored in the memory, wherein the bias state is associated with control of access for the set of data by the host device. ### Claim 25 (depends on 24) The method of claim 24, wherein the coherency state for the set of data is stored independent from the command, the method further comprising: transmitting, to the host device, an indication of the access operation to be performed on the set of data based at least in part on determining to process the command according to the bias state; and receiving, from the host device, a second command for indicating direct access for the set of data for the access operation based at least in part on transmitting the indication of the access operation. ### Claim 26 (depends on 25) The method of claim 25, wherein the command comprises a read command, the method further comprising: accessing the memory for the set of data based at least in part on receiving the second command from the host device. ### Claim 27 (depends on 26) The method of claim 26, further comprising: transmitting the set of data received from the host device to the memory based at least in part on receiving the set of data from the host device. ### Claim 28 (depends on 24) The method of claim 24, wherein the memory is configured to store a first value that is associated with a first coherency state for the set of data, a second value that is associated with a second coherency state for the set of data, or a third value that is associated with a third coherency state for the set of data. ### Claim 29 (depends on 28) The method of claim 28, wherein: the first value indicates that an invalid version of the set of data is stored to the cache of the host device; the second value indicates that a shared version or an exclusive version of the set of data is stored to the cache of the host device; and the third value indicates that the shared version of the set of data is stored to the cache of the host device. ### Claim 30 (depends on 28) The method of claim 28, wherein the second value and the third value indicate that the set of data is coherent, and wherein the command is processed according to the bias state based at least in part on the memory storing the second value or the third value for the set of data. ### Claim 31 (depends on 24) The method of claim 24, wherein the set of data is associated with a first quantity of data, and wherein a cache line of the host device coupled with the memory is configured to store the first quantity of data. ### Claim 32 (depends on 24) The method of claim 24, wherein a first bias state is associated with control of access for the set of data by the controller, and wherein the bias state corresponds to a second bias state. ### Claim 33 A non-transitory computer-readable medium storing code comprising instructions, which when executed by a processor of an electronic device, cause the electronic device to: store a coherency state for a set of data stored in a memory relative to a cache of a host device; and access the memory according to a bias state for the set of data determined based at least in part on the stored coherency state for the set of data based at least in part on identifying a command to perform an access operation for the set of data stored in the memory, wherein the bias state is associated with control of access for the set of data by a controller associated with the memory.