# US 11,442,856 B2 · Virtualized caches

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,442,856 B2
- Document ID: US11442856B2
- Status: Granted
- Kind: B2
- Application number: 17/103,856
- Filed: 2020-11-24
- Published: 2021-05-27
- Granted: 2022-09-13
- Earliest claimed: 2019-11-25
- Assignees: SiFive, Inc.
- Applicants: SiFive, Inc.
- Inventors: Wesley Waylon Terpstra
- Web page: https://patentgrep.com/patent/US11442856B2

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/1063: {the data cache being concurrently virtually addressed}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0815: Cache consistency protocols
- G06F 12/0848: {Partitioned cache, e.g. separate instruction and operand caches}
- G06F 12/0882: Page mode
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

## Claims

### Claim 1

An integrated circuit comprising:
a virtually indexed cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier, receive one or more bits of a destination identifier for a probe request from the outer memory system, and use the one or more bits of the destination identifier as part of an index to check a state of a cache block.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, in which the virtually indexed cache is a virtually indexed L1 cache, and further comprising:
an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed L1 cache associated with different requestor identifier values.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, in which the L2 cache includes ownership bits that respectively correspond to each of the multiple portions of the virtually indexed L1 cache associated with different requestor identifier values.

### Claim 4 (depends on 2)

The integrated circuit of claim 2, in which the L2 cache is directory-based.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, in which a size of a cache way in the virtually indexed cache is equal to twice a virtual memory page size used by a core of the integrated circuit associated with the virtually indexed cache, and the one or more bits of the virtual index are a single bit.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, in which a size of a cache way in the virtually indexed cache is equal to four times a virtual memory page size used by a core of the integrated circuit associated with the virtually indexed cache, and the one or more bits of the virtual index are two bits.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, in which the virtually indexed cache is a data cache.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, in which the virtually indexed cache is an instruction cache.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, in which the virtually indexed cache is a virtually indexed physically tagged L1 cache.

### Claim 10

A method comprising:
outputting to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier;
receiving one or more bits of a destination identifier for a probe request from the outer memory system; and
using the one or more bits of the destination identifier as part of an index to check a state of a cache block.

### Claim 11 (depends on 10)

The method of claim 10, in which the request identifier is output from a virtually indexed L1 cache, and further comprising:
receiving the requestor identifier at an L2 cache of the outer memory system; and
implementing a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed L1 cache associated with different requestor identifier values.

### Claim 12 (depends on 11)

The method of claim 11, in which the L2 cache includes ownership bits that respectively correspond to each of the multiple portions of the virtually indexed L1 cache associated with different requestor identifier values.

### Claim 13 (depends on 11)

The method of claim 11, in which the virtually indexed L1 cache is a virtually indexed physically tagged L1 cache.

### Claim 14 (depends on 11)

The method of claim 11, in which a size of a cache way in the virtually indexed L1 cache is equal to twice a virtual memory page size used by a core associated with the virtually indexed L1 cache, and the one or more bits of the virtual index are a single bit.

### Claim 15 (depends on 11)

The method of claim 11, in which a size of a cache way in the virtually indexed L1 cache is equal to four times a virtual memory page size used by a core associated with the virtually indexed L1 cache, and the one or more bits of the virtual index are two bits.