# US 11,442,851 B2 · Processing-in-memory and method and apparatus with memory access

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- Number: US 11,442,851 B2
- Document ID: US11442851B2
- Status: Granted
- Kind: B2
- Application number: 17/201,539
- Filed: 2021-03-15
- Published: 2022-03-10
- Granted: 2022-09-13
- Earliest claimed: 2021-03-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hosang Yoon; Seungwon Lee
- Web page: https://patentgrep.com/patent/US11442851B2

## CPC

- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0673: {Single storage device}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30101: {Special purpose registers}
- G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/1054: {the data cache being concurrently physically addressed}
- G06F 12/1063: {the data cache being concurrently virtually addressed}
- G06F 2212/1024: Latency reduction
- G06F 2212/1056: Simplification
- G06F 2212/72: Details relating to flash memory management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing-in-memory includes: a memory; a register configured to store offset information; and an internal processor configured to: receive an instruction and a reference physical address of the memory from a memory controller, determine an offset physical address of the memory based on the offset information, determine a target physical address of the memory based on the reference physical address and the offset physical address, and perform the instruction by accessing the target physical address.

## Claims

### Claim 1

A processing-in-memory, comprising:
a memory;
a register configured to store offset information; and
an internal processor configured to:
receive an instruction and a reference physical address of the memory from a memory controller,
determine an offset physical address of the memory based on the offset information,
determine a target physical address of the memory based on the reference physical address and the offset physical address, and
perform the instruction by accessing the target physical address.

### Claim 2 (depends on 1)

The processing-in-memory of claim 1, further comprising:
a cache configured to store the offset information and the target physical address.

### Claim 3 (depends on 2)

The processing-in-memory of claim 2, wherein the internal processor is further configured to:
search the cache based on the offset information, and
perform the instruction by accessing the target physical address in response to the target physical address corresponding to the offset information being found in the cache by the search.

### Claim 4 (depends on 3)

The processing-in-memory of claim 3, wherein, for the determining of the target physical address, the internal processor is further configured to:
determine the target physical address based on the reference physical address and the offset physical address in response to the target physical address corresponding to the offset information not being found in the cache by the search.

### Claim 5 (depends on 1)

The processing-in-memory of claim 1, wherein, for the performing of the instruction, the internal processor is further configured to perform a processing-in-memory (PIM) operation based on information stored in the memory at the target physical address.

### Claim 6 (depends on 1)

The processing-in-memory of claim 1, wherein the reference physical address corresponds to an absolute location in the memory, and the offset physical address corresponds to a relative location indicating a distance to the reference physical address in the memory.

### Claim 7 (depends on 1)

A memory access apparatus, comprising:
the processing-in-memory of claim 1;
the memory controller of claim 1;
an external processor configured to transmit the offset information of claim 1 to the processing-in-memory of claim 1; and
a memory management unit (MMU) configured to transmit the reference physical address of claim 1 to the memory controller of claim 1.

### Claim 8

A memory access apparatus, comprising:
a processing-in-memory comprising an internal processor, a memory, and a register;
a memory controller;
an external processor; and
a memory management unit (MMU),
wherein the external processor is configured to transmit offset information to the processing-in-memory, transmit an instruction to the memory controller, and transmit a reference virtual address to the MMU,
wherein the MMU is configured to convert the reference virtual address into a reference physical address of the memory, and transmit the reference physical address to the memory controller,
wherein the register is configured to store the transmitted offset information, and
wherein the internal processor is configured to:
receive the instruction and the reference physical address from the memory controller,
determine an offset physical address of the memory based on the offset information,
determine a target physical address of the memory based on the reference physical address and the offset physical address, and
perform the instruction by accessing the target physical address.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the processing-in-memory further comprises a cache configured to store the offset information and the target physical address.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the internal processor is further configured to:
search the cache based on the offset information, and
perform the instruction by accessing the target physical address in response to the target physical address corresponding to the offset information being found in the cache by the search.

### Claim 11

A memory access method of a processing-in-memory, the method comprising:
receiving, by an internal processor, an instruction and a reference physical address of a memory from a memory controller;
determining, by the internal processor, an offset physical address of the memory based on offset information stored in a register;
determining, by the internal processor, a target physical address of the memory based on the reference physical address and the offset physical address; and
performing, by the internal processor, the instruction by accessing the target physical address.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
storing the offset information and the target physical address in a cache included in the processing-in-memory.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
searching, by the internal processor, the cache based on the offset information; and
performing, by the internal processor, the instruction by accessing the target physical address in response to the target physical address corresponding to the offset information being found in the cache by the search.

### Claim 14 (depends on 11)

A non-transitory computer-readable storage medium storing instructions that, when executed by an external processor, configure the external processor to perform the method of claim 11.

### Claim 15

A memory access method of a processing apparatus, the method comprising:
transmitting, by an external processor, offset information to a processing-in-memory, transmitting an instruction to a memory controller, and transmitting a reference virtual address to a memory management unit (MMU);
converting, by the MMU, the reference virtual address into a reference physical address of a memory, and transmitting, by the MMU, the reference physical address to the memory controller;
storing, by a register, the offset information;
receiving, by an internal processor, the instruction and the reference physical address from the memory controller;
determining, by the internal processor, an offset physical address of the memory based on the offset information;
determining, by the internal processor, a target physical address of the memory based on the reference physical address and the offset physical address; and
performing, by the internal processor, the instruction by accessing the target physical address.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
storing, by a cache included in the processing-in-memory, the offset information and the target physical address.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
searching, by the internal processor, the cache based on the offset information; and
performing, by the internal processor, the instruction by accessing the target physical address in response to the target physical address corresponding to the offset information being found in the cache by the search.