# US 11,442,829 B2 · Packeted protocol device test system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,829 B2 - Document ID: US11442829B2 - Status: Granted - Kind: B2 - Application number: 16/819,512 - Filed: 2020-03-16 - Published: 2021-09-16 - Granted: 2022-09-13 - Earliest claimed: 2020-03-16 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Ryan Patrick King; Kevin M. Mcilvain; Gary A. Van Huben - Web page: https://patentgrep.com/patent/US11442829B2 ## CPC - G06F 11/27: Built-in tests - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases. ## Claims ### Claim 1 A method comprising: configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test; arbitrating test traffic between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device, the arbitrating comprising routing the test traffic through an interconnect backbone of the test control device to an arbiter associated with one of the packeted protocol layer interfaces, wherein the arbiter comprises circuitry of the test control device that receives traffic from multiple sources and selects and limits traffic flow to the one of the packeted protocol layer interfaces; performing one or more protocol specific conversions between the test traffic and a device-specific packeted protocol of each of the devices under test; and performing payload checking between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases. ### Claim 2 (depends on 1) The method of claim 1, further comprising: servicing an access portal to support an alternate path to pass through the packeted protocol layer interfaces to the devices under test independently of the functional self-test controllers; and converting, by a response handler of the test control device, a response from the packeted protocol layer interfaces into a format compatible with the access portal prior to outputting the response to the access portal. ### Claim 3 (depends on 1) The method of claim 1, wherein the test control device comprises a plurality of arbiters each coupled to the interconnect backbone and a different one of the packeted protocol layer interfaces. ### Claim 4 (depends on 3) The method of claim 3, further comprising: interfacing an access portal with the interconnect backbone, the access portal providing an external interface to the test control device. ### Claim 5 (depends on 3) The method of claim 3, further comprising: mixing, at the arbiter, the test traffic from the interconnect backbone with one or more commands issued by a configured command sequencer of the test control device, wherein the configured command sequencer comprises a programmable array. ### Claim 6 (depends on 5) The method of claim 5, wherein the configured command sequencer is configurable to execute a sequence of tests. ### Claim 7 (depends on 3) The method of claim 3, further comprising: providing a response from the packeted protocol layer interfaces to the interconnect backbone. ### Claim 8 (depends on 3) The method of claim 3, further comprising: configuring the test control device based on a microcontroller executing a plurality of instructions, wherein the microcontroller is coupled to the interconnect backbone; and collecting a plurality of test results in a system memory, wherein the system memory is coupled to the interconnect backbone. ### Claim 9 (depends on 1) The method of claim 1, further comprising: configuring a direct memory access controller of the test control device to interact with at least one of the packeted protocol layer interfaces. ### Claim 10 A test control device comprising: a plurality of functional self-test controllers configured to generate test traffic as part of running a plurality of functional test cases in parallel on a plurality of devices under test; an interconnect backbone coupled to the functional self-test controllers; a plurality of arbiters coupled to the interconnect backbone; a plurality of packeted protocol layer interfaces coupled to the arbiters, wherein the packeted protocol layer interfaces are configured to perform one or more protocol specific conversions between the test traffic and a device-specific packeted protocol of each of the devices under test, and further wherein the arbiters comprise circuitry that receives traffic from multiple sources and selects and limits traffic flow to the packeted protocol layer interfaces; and a plurality of payload checkers configured to verify responses of the devices under test to the functional test cases. ### Claim 11 (depends on 10) The test control device of claim 10, wherein the packeted protocol layer interfaces are configured to communicate with the devices under test on separate high-speed serial communication links. ### Claim 12 (depends on 10) The test control device of claim 10, further comprising: an access portal to support an alternate path to pass through the packeted protocol layer interfaces to the devices under test independently of the functional self-test controllers. ### Claim 13 (depends on 10) The test control device of claim 10, further comprising: a configured command sequencer coupled to the interconnect backbone, the configured command sequencer operable to issue one or more commands to mix with the test traffic by the arbiters as part of executing a sequence of tests, wherein the configured command sequencer comprises a programmable array. ### Claim 14 (depends on 10) The test control device of claim 10, further comprising: a microcontroller coupled to the interconnect backbone, wherein the microcontroller is operable to execute a plurality of instructions to configure the test control device; and a system memory coupled to the interconnect backbone, the system memory operable to collect a plurality of test results. ### Claim 15 (depends on 10) The test control device of claim 10, further comprising: a direct memory access controller configurable to interact with at least one of the packeted protocol layer interfaces. ### Claim 16 A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to perform a plurality of operations comprising: configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test; arbitrating test traffic between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device, the arbitrating comprising routing the test traffic through an interconnect backbone of the test control device to an arbiter associated with one of the packeted protocol layer interfaces, wherein the arbiter comprises circuitry of the test control device that receives traffic from multiple sources and selects and limits traffic flow to the one of the packeted protocol layer interfaces; performing one or more protocol specific conversions between the test traffic and a device-specific packeted protocol of each of the devices under test; and performing payload checking between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases. ### Claim 17 (depends on 16) The computer program product of claim 16, wherein the operations further comprise: servicing an access portal to support an alternate path to pass through the packeted protocol layer interfaces to the devices under test independently of the functional self-test controllers. ### Claim 18 (depends on 16) The computer program product of claim 16, wherein the operations further comprise: mixing, at the arbiter, the test traffic from the interconnect backbone with one or more commands issued by a configured command sequencer of the test control device, wherein the configured command sequencer comprises a programmable array configurable to execute a sequence of tests. ### Claim 19 (depends on 18) The computer program product of claim 18, wherein the operations further comprise: collecting a plurality of test results in a system memory, wherein the system memory is coupled to the interconnect backbone. ### Claim 20 (depends on 16) The computer program product of claim 16, wherein the operations further comprise: configuring a direct memory access controller of the test control device to interact with at least one of the packeted protocol layer interfaces.