# US 11,442,810 B2 · Memory and operation method of memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,810 B2 - Document ID: US11442810B2 - Status: Granted - Kind: B2 - Application number: 17/330,881 - Filed: 2021-05-26 - Published: 2021-12-23 - Granted: 2022-09-13 - Earliest claimed: 2020-06-22 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Munseon Jang; Hoiju Chung; Jang Ryul Kim - Web page: https://patentgrep.com/patent/US11442810B2 ## CPC - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} - H03M 13/616: {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A memory includes: a memory core including sequentially disposed N data cell regions and an ECC cell region respectively suitable for storing N data pieces of K bits and a corresponding ECC of M bits; and an error correction circuitry suitable for generating the ECC based on the data pieces and error-correcting the data pieces based on the ECC, through a check matrix configured by a message part of a [M×(K*N)] bit-dimension and an ECC part of a [M×M] bit-dimension, wherein the message part includes N characteristic indicator groups of a [M/2×K] bit-dimension, respectively corresponding to the data pieces, and each including K indicators of a [M/2×1] bit-dimension and having the same value, and wherein a hamming distance between the indicators respectively corresponding to the data pieces stored in neighboring ones among the data cell regions is 1 or M/2. ## Claims ### Claim 1 A memory, comprising: an error correction code generation circuit configured to generate an M-bit error correction code based on a message including N data groups each of which includes K-bit data, where K, N and M are positive integers; a memory core including N+1 cell regions for storing the N data groups and the error correction code; and an error correction circuit configured to correct errors of the N data groups that are read from the memory core based on the M-bit error correction code that is read from the memory core, wherein the error correction code generation circuit generates the M-bit error correction code based on a message for an M×[(K*N)+M] check matrix, wherein the message of the M×[(K*N)+M] check matrix includes N group indicators distinguishing the N data groups, and N parts of bit indicators each of which distinguishes the K-bit data in a corresponding one of the N data groups, and wherein a hamming distance between the N group indicators respectively corresponding to neighboring data groups among the N group indicators is 1 or M/2. ### Claim 2 (depends on 1) The memory of claim 1, wherein the neighboring data groups are the data groups stored in neighboring cell regions among the cell regions. ### Claim 3 (depends on 2) The memory of claim 2, wherein the neighboring cell regions share at least one sub-word line driver or more. ### Claim 4 (depends on 1) The memory of claim 1, wherein each of the N group indicators has a size of (M/2)×K, and wherein each of the N parts of bit indicators has a size of (M/2)×K. ### Claim 5 (depends on 1) The memory of claim 1, wherein each of the N data groups is input to the memory through a different data pad. ### Claim 6 A method for operating a memory, comprising: receiving N data groups each of which includes K-bit data, where K and N are positive integers; generating an M-bit error correction code by using the N data groups as a message, where M is a positive integer; and storing the N data groups and the M-bit error correction code in N+1 cell regions of a memory core, wherein the M-bit error correction code is generated based on a message for an M×[(K*N)+M] check matrix, wherein the message of the M×[(K*N)+M] check matrix includes N group indicators distinguishing the N groups, and N parts of bit indicators each of which distinguishes the K-bit data groups in a corresponding one of the N data groups, and wherein a hamming distance between the N group indicators respectively corresponding to neighboring data groups among the N group indicators is 1 or M/2. ### Claim 7 (depends on 6) The method of claim 6, wherein the neighboring data groups are the data groups stored in neighboring cell regions among the cell regions. ### Claim 8 (depends on 7) The method of claim 7, wherein the neighboring cell regions share at least one sub-word line driver or more. ### Claim 9 (depends on 6) The method of claim 6, wherein each of the N group indicators has a size of (M/2)×K, and wherein each of the N parts of bit indicators has a size of (M/2)×K. ### Claim 10 (depends on 6) The method of claim 6, wherein the receiving includes receiving each of the N data groups through a different data pad. ### Claim 11 (depends on 6) The method of claim 6, further comprising correcting errors of the N data groups that are read from the memory core based on the error correction code that is read from the memory core. ### Claim 12 A memory, comprising: an error correction code generation circuit configured to generate an 8-bit error correction code based on a message including 8 data groups each of which includes 16-bit data; a memory core including 9 cell regions for storing the 8 data groups and the 8-bit error correction code; and an error correction circuit configured to correct errors of the 8 data groups that are read from the memory core based on the 8-bit error correction code that is read from the memory core, wherein the error correction code generation circuit generates the 8-bit error correction code based on a message for an 8×136 check matrix, wherein the message of the 8×136 check matrix includes 8 group indicators distinguishing the 8 data groups, and 8 parts of bit indicators each of which distinguishes the 16-bit data in a corresponding one of the 8 data groups, and wherein a hamming distance between the 8 group indicators respectively corresponding to neighboring data groups among the 8 group indicators is 1 or 4. ### Claim 13 (depends on 12) The memory of claim 12, wherein the neighboring data groups are the data groups stored in neighboring cell regions among the cell regions. ### Claim 14 (depends on 13) The memory of claim 13, wherein the neighboring cell regions share at least one sub-word line driver or more. ### Claim 15 (depends on 12) The memory of claim 12, wherein each of the 8 group indicators has a size of 4×16, and wherein each of the 8 parts of bit indicators has a size of 4×16. ### Claim 16 (depends on 12) The memory of claim 12, wherein each of the 8 data groups is input to the memory through a different data pad. ### Claim 17 A memory, comprising: an error correction code generation circuit configured to generate an M-bit error correction code based on a message including N data groups each of which includes K-bit data, where K, N and M are positive integers; a memory core including N+1 cell regions for storing the N data groups and the M-bit error correction code; and an error correction circuit configured to correct errors of the N data groups that are read from the memory core based on the M-bit error correction code that is read from the memory core, wherein the error correction code generation circuit generates the M-bit error correction code based on a message for an M×[(K*N)+M] check matrix, wherein the message part of the M×[(K*N)+M] check matrix includes N group indicators distinguishing the N data groups, and N parts of bit indicators each of which distinguishes the K-bit data in a corresponding one of the N data groups, and wherein a sum of the N group indicators respectively corresponding to neighboring data groups among the N group indicators is different from any of the N group indicators.