# US 11,442,808 B2 · Memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,442,808 B2 - Document ID: US11442808B2 - Status: Granted - Kind: B2 - Application number: 17/198,451 - Filed: 2021-03-11 - Published: 2021-09-16 - Granted: 2022-09-13 - Earliest claimed: 2020-03-12 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takehiko Amaki; Toshikatsu Hida; Shunichi Igahara; Yoshihisa Kojima; Suguru Nishikawa - Web page: https://patentgrep.com/patent/US11442808B2 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0891: using clearing, invalidating or resetting means - G06F 12/1458: {by checking the subject access rights} - G06F 2212/1052: Security improvement - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory. ## Claims ### Claim 1 A memory system comprising: a nonvolatile memory; a random access memory; and a controller configured to control the nonvolatile memory and the random access memory, wherein the controller is configured to: generate a first error correction code that constitutes an error correction code frame of a first size together with a data portion of a first unit to be written into the nonvolatile memory by encoding the data portion of the first unit, write the data portion of the first unit into the nonvolatile memory, and write the first error correction code into the nonvolatile memory or store the first error correction code in the random access memory; and when writing n−1 data portions of the first unit that are included in n−1 error correction code frames of the first size, respectively, in the nonvolatile memory, generate a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and write the second data portion and the second error correction code into the nonvolatile memory, wherein n is an integer greater than one. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the controller is further configured to set, in an invalid state, each of n−1 error correction codes that are stored in the nonvolatile memory or the random access memory and are included in the n−1 error correction code frames of the first size, respectively, after writing the second data portion and the second error correction code into the nonvolatile memory. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the controller is configured to set each of the n−1 error correction codes in the invalid state by deleting, from first information including second information pieces each indicative of an address in the nonvolatile memory or an address in the random access memory in which an error correction code is stored, n−1 second information pieces that correspond to the n−1 error correction codes, respectively. ### Claim 4 (depends on 2) The memory system of claim 2, wherein the controller is configured to set each of the n−1 error correction codes in the invalid state by changing, in third information including fourth information pieces each indicative of validity or invalidity of an error correction code, n−1 fourth information pieces that correspond to the n−1 error correction codes, respectively, from valid to invalid. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the controller is further configured to: when erasing a third data portion of the first unit that is included in an error correction code frame of the second size and is stored in the nonvolatile memory, generate a third error correction code corresponding to the third data portion; and write the third error correction code into the nonvolatile memory or store the third error correction code in the random access memory. ### Claim 6 (depends on 5) The memory system of claim 5, wherein the controller is further configured to: read a fourth data portion included in an error correction code frame of the second size from the nonvolatile memory; and when an error occurs in the read fourth data portion, perform error correction processing on a data portion in the error correction code frame of the second size excluding the third data portion by using a fourth error correction code obtained by subtracting the third error correction code from the second error correction code. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the controller is configured to detect the error which occurs in the read fourth data portion by using an error correction code included in the fourth data portion. ### Claim 8 (depends on 1) The memory system of claim 1, wherein the controller is further configured to: read part or all of a fifth data portion of the first unit from the nonvolatile memory; and when an error occurs in the read part or all of the fifth data portion, perform error correction processing on the fifth data portion by using the first error correction code that constitutes an error correction code frame of the first size together with the fifth data portion. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the controller is further configured to perform, when writing of part or all of a sixth data portion of the first unit into the nonvolatile memory is not successful, error correction processing on the sixth data portion by using the first error correction code that constitutes an error correction code frame of the first size together with the sixth data portion. ### Claim 10 (depends on 1) The memory system of claim 1, wherein the nonvolatile memory includes n first physical blocks and a second physical block, and the controller is further configured to: generate the first error correction code that constitutes the error correction code frame of the first size together with the data portion of the first unit to be written into the nonvolatile memory by encoding the data portion of the first unit, write the data portion of the first unit to one of the n first physical blocks, and write the first error correction code to the second physical block or store the first error correction code in the random access memory; and when writing the n−1 data portions of the first unit which are included in the n−1 error correction code frames of the first size, respectively, in n−1 physical blocks of the n first physical blocks, generate the second error correction code that constitutes the error correction code frame of the second size together with the n−1 data portions of the first unit and the second data portion to be written to a remaining third physical block of the n physical blocks by encoding the n−1 data portions of the first unit and the second data portion, and write the second data portion and the second error correction code to the third physical block. ### Claim 11 (depends on 10) The memory system of claim 10, wherein the controller is further configured to set, in an invalid state, each of n−1 error correction codes that are stored in the second physical block or the random access memory and are included in the n−1 error correction code frames of the first size, respectively, after writing the second data portion and the second error correction code to the third physical block. ### Claim 12 (depends on 10) The memory system of claim 10, wherein the controller is further configured to: when erasing a third data portion of the first unit in the error correction code frame of the second size from a fourth physical block of the n first physical blocks, generate a third error correction code corresponding to the third data portion; and write the third error correction code to the second physical block or store the third error correction code in the random access memory. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the controller is further configured to: read a fourth data portion in an error correction code frame of the second size from one of n−1 fifth physical blocks that are obtained by excluding the fourth physical block from the n first physical blocks; and perform error correction processing on a data portion that is included in the error correction code frame of the second size and is stored in the n−1 fifth physical blocks by using a fourth error correction code obtained by subtracting the third error correction code from the second error correction code, when an error occurs in the read fourth data portion. ### Claim 14 (depends on 1) The memory system of claim 1, wherein the nonvolatile memory includes physical blocks, the controller further manages logical blocks each including a set of physical blocks, a first logical block of the logical blocks includes n logical storage areas, each of the n logical storage areas corresponds to the first unit, the controller is further configured to: generate the first error correction code that constitutes the error correction code frame of the first size together with the data portion of the first unit to be written into the nonvolatile memory by encoding the data portion of the first unit, write the data portion of the first unit into one of the n logical storage areas, and write the first error correction code into a second logical block of the logical blocks or a first physical block of the physical blocks or store the first error correction code in the random access memory; and when writing the n−1 data portions of the first unit that are included in the n−1 error correction code frames of the first size, respectively, are written in n−1 logical storage areas of the n logical storage areas, respectively, generate the second error correction code that constitutes the error correction code frame of the second size together with the n−1 data portions of the first unit and the second data portion to be written into a remaining first logical storage area of the n logical storage areas by encoding the n−1 data portions of the first unit and the second data portion, and write the second data portion and the second error correction code into the first logical storage area. ### Claim 15 (depends on 14) The memory system of claim 14, wherein the controller is further configured to set, in an invalid state, each of n−1 error correction codes that are included in the n−1 first size error correction code frames, respectively, and are stored in one of the second logical block, the first physical block and the random access memory, after writing the second data portion and the second error correction code into the first logical storage area. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the controller is further configured to: read the n−1 data portions of the first unit, the second data portion and the second error correction code from the n logical storage areas, after writing the second data portion and the second error correction code into the first logical storage area; and set, in an invalid state, the n−1 error correction codes that are included in the n−1 error correction code frames of the first size, respectively, and are stored in one of the second logical block, the first physical block and the random access memory, when integrity of the read n−1 data portions of the first unit, the second data portion and the second error correction code is confirmed. ### Claim 17 (depends on 14) The memory system of claim 14, wherein the first error correction code is equal to the second error correction code in data length. ### Claim 18 (depends on 14) The memory system of claim 14, wherein the first unit corresponds to a data unit that is able to be written in a parallel write operation. ### Claim 19 (depends on 14) The memory system of claim 14, wherein each of the n logical storage areas corresponds to a logical word line string chunk. ### Claim 20 (depends on 14) The memory system of claim 14, wherein the first logical block includes n physical blocks, each of the n logical storage areas is composed of n storage areas that are included in the n physical blocks, respectively, and the controller is further configured to be able to write, in parallel, data to the n storage areas. ### Claim 21 (depends on 1) The memory system of claim 1, wherein the first error correction code and the second error correction code are both linear codes. ### Claim 22 (depends on 1) The memory system of claim 1, wherein the second data portion has a size obtained by subtracting a size of the second error correction code from a size of the data portion of the first unit.